4,251 research outputs found
A design tool for high-resolution high-frequency cascade continuous- time ÎŁâ modulators
Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran
Canaria, SpainThis paper introduces a CAD methodology to assist the de
signer in the implementation of continuous-time (CT) cas-
cade
ÎŁâ
modulators. The salient features of this methodology ar
e: (a) flexible behavioral modeling for optimum accuracy-
efficiency trade-offs at different stages of the top-down
synthesis process; (b) direct synthesis in the continuous-time
domain for minimum circuit complexity and sensitivity; a
nd (c) mixed knowledge-based and optimization-based architec-
tural exploration and specification transmission for enhanced
circuit performance. The applicability of this methodology
will be illustrated via the design of a 12 bit 20 MHz CT
ÎŁâ
modulator in a 1.2V 130nm CMOS technology.Ministerio de Ciencia y EducaciĂłn TEC2004-01752/MICMinisterio de Industria, Turismo y Comercio FIT-330100-2006-134 SPIRIT Projec
Force feedback linearization for higher-order electromechanical sigma-delta modulators.
Abstract A higher-order electromechanical sigmaâdelta modulator can greatly improve the signal-to-noise ratio compared with a second-order loop that only uses the sensing element as a loop filter. However, the electrostatic force feedback on the proof mass is inherently nonlinear, which will produce harmonics in the output spectrum and limits the total signal-to-noise and distortion ratio. High performance inertial sensors, which use sigmaâdelta modulators as a closed-loop control system, have strict requirements on the output signal distortion. In this paper, nonlinear effects from the force feedback and pick-off circuits are analysed and a strategy for force feedback linearization is put forward which can considerably improve the signal-to-noise and distortion ratio. A PCB prototype of a fifth-order electromechanical modulator with a bulk micromachined accelerometer was used to demonstrate the concept
Adaptive design of delta sigma modulators
In this thesis, a genetic algorithm based on differential evolution (DE) is used to generate delta sigma modulator (DSM) noise transfer functions (NTFs). These NTFs outperform those generated by an iterative approach described by Schreier and implemented in the delsig Matlab toolbox. Several lowpass and bandpass DSMs, as well as DSM\u27s designed specifically for and very low intermediate frequency (VLIF) receivers are designed using the algorithm developed in this thesis and compared to designs made using the delsig toolbox. The NTFs designed using the DE algorithm always have a higher dynamic range and signal to noise ratio than those designed using the delsig toolbox
Prediction of the Spectrum of a Digital DeltaâSigma Modulator Followed by a Polynomial Nonlinearity
This paper presents a mathematical analysis of the power spectral density of the output of a nonlinear block driven by a digital delta-sigma modulator. The nonlinearity is a memoryless third-order polynomial with real coefficients. The analysis yields expressions that predict the noise floor caused by the nonlinearity when the input is constant
Contribución al modelado y diseño de moduladores sigma-delta en tiempo continuo de baja relación de sobremuestreo y bajo consumo de potencia
Continuous-Time Sigma-Delta modulators are often employed as analog-to-digital converters. These modulators are an attractive approach to implement high-speed converters in VLSI systems because they have low sensitivity to circuit imperfections compared to other solutions. This work is a contribution to the analysis, modelling and design of high-speed Continuous-Time Sigma-Delta modulators. The resolution and the stability of these modulators are limited by two main factors, excess-loop delay and sampling uncertainty. Both factors, among others, have been carefully analysed and modelled. A new design methodology is also proposed. It can be used to get an optimum high-speed Continuous-Time Sigma-Delta modulator in terms of dynamic range, stability and sensitivity to sampling uncertainty. Based on the proposed design methodology, a software tool that covers the main steps has been developed. The methodology has been proved by using the tool in designing a 30 Megabits-per-second Continuous-Time Sigma-Delta modulator with 11-bits of dynamic range. The modulator has been integrated in a 0.13-”m CMOS technology and it has a measured peak SNR of 62.5dB
Output Filter Aware Optimization of the Noise Shaping Properties of {\Delta}{\Sigma} Modulators via Semi-Definite Programming
The Noise Transfer Function (NTF) of {\Delta}{\Sigma} modulators is typically
designed after the features of the input signal. We suggest that in many
applications, and notably those involving D/D and D/A conversion or actuation,
the NTF should instead be shaped after the properties of the
output/reconstruction filter. To this aim, we propose a framework for optimal
design based on the Kalman-Yakubovich-Popov (KYP) lemma and semi-definite
programming. Some examples illustrate how in practical cases the proposed
strategy can outperform more standard approaches.Comment: 14 pages, 18 figures, journal. Code accompanying the paper is
available at http://pydsm.googlecode.co
Comparison of Simulation Methods of Single and Multi-Bit Continuous Time Sigma Delta Modulators
Continuous time Sigma Delta Modulators (CT ÎŁÎMs) are a type of analog to digital converter (ADC) that are used in mixed signal systems to convert analog signals into digital signals. ADCs typically require antialiasing filter; however antialiasing filters are inherent in CT ÎŁÎMs, and therefore they require less circuitry and less power than other ADC architectures that require separate antialiasing filters. As a result, CT ÎŁÎM ADC architectures are preferred in many mixed signal electronic applications.
Because of the mixed signal nature of CT ÎŁÎMs, they can be difficult to simulate. In this thesis, various methods for simulating single-bit and multi-bit CT ÎŁÎMs are developed and these simulations include the bilinear transform or trapezoidal integration, impulse invariance transform, midpoint integration, Simpsonâs rule, delta transform or Eulerâs forward integration rule and Simulink modeling. These methods are compared with respect to speed which is given by the total simulation time, accuracy which is given by the signal to noise ratio (SNR) value and the simplicity of the simulation method. The CT ÎŁÎMs have been extended from first order up to fifth order with one, two and three bit quantizers. Also, the frequency domain analysis is done for all the orders of CT ÎŁÎMs.
The results show that the numerical integration methods are more accurate and faster than Simulink. However, CT ÎŁÎM simulations using Simulink are simpler because of the availability of the required blocks in Simulink. The overall comparison shows that the numerical integration methods can perform better than Simulink models. The frequency domain analysis proves the correctness of the use of numerical integration methods for CT ÎŁÎM simulations
Design and implementation of a wideband sigma delta ADC
Abstract. High-speed and wideband ADCs have become increasingly important in response to the growing demand for high-speed wireless communication services. Continuous time sigma delta modulators (CTÆ©âM), well-known for their oversampling and noise shaping properties, offer a promising solution for low-power and high-speed design in wireless applications.
The objective of this thesis is to design and implement a wideband CTÆ©âM for a global navigation satellite system(GNSS) receiver. The targeted modulator architecture is a 3rdorder single-bit CTÆ©âM, specifically designed to operate within a 15 MHz signal bandwidth. With an oversampling ratio of 25, the ADCâs sampling frequency is set at 768 MHz. The design goal is to achieve a theoretical signal to noise ratio (SNR) of 55 dB.
This thesis focuses on the design and implementation of the CTÆ©âM, building upon the principles of a discrete time Æ©â modulator, and leveraging system-level simulation and formulations. A detailed explanation of the coefficient calculation procedure specific to CTÆ©â modulators is provided, along with a "top-down" design approach that ensures the specified requirements are met. MATLAB scripts for coefficient calculation are also included. To overcome the challenges associated with the implementation of CTÆ©â modulators, particularly excess loop delay and clock jitter sensitivity, this thesis explores two key strategies: the introduction of a delay compensation path and the utilization of a finite impulse response (FIR) feedback DAC. By incorporating a delay compensation path, the stability of the modulator can be ensured and its noise transfer function (NTF) can be restored. Additionally, the integration of an FIR feedback DAC addresses the issue of clock jitter sensitivity, enhancing the overall performance and robustness of the CTÆ©âM.
The CTÆ©âMs employ the cascade of integrators with feed forward (CIFF) and cascade of integrators with feedforward and feedback (CIFF-B) topologies, with a particular emphasis on the CIFF-B configuration using 22nm CMOS technology node and a supply voltage of 0.8 V. Various simulations are performed to validate the modulatorâs performance. The simulation results demonstrate an achievable SNR of 55 dB with a power consumption of 1.36 mW. Furthermore, the adoption of NTF zero optimization techniques enhances the SNR to 62 dB.Laajakaistaisen jatkuva-aikaisen sigma delta-AD-muuntimen suunnittelu ja toteutus. TiivistelmĂ€. Nopeat ja laajakaistaiset AD-muuntimet ovat tulleet entistĂ€ tĂ€rkeĂ€mmiksi nopeiden langattomien kommunikaatiopalvelujen kysynnĂ€n kasvaessa. Jatkuva-aikaiset sigma delta -modulaattorit (CTÆ©âM), joissa kĂ€ytetÀÀn ylinĂ€ytteistystĂ€ ja kohinanmuokkausta, tarjoavat lupaavan ratkaisun matalan tehonkulutuksen ja nopeiden langattomien sovellusten suunnitteluun.
TĂ€mĂ€n työn tarkoituksena on suunnitella ja toteuttaa laajakaistainen jatkuva -aikainen sigma delta -modulaattori satelliittipaikannusjĂ€rjestelmien (GNSS) vastaanottimeen. Arkkitehtuuriltaan modulaattori on kolmannen asteen 1-bittinen CTÆ©âM, jolla on 15MHz:n signaalikaistanleveys. YlinĂ€ytteistyssuhde on 25 ja AD muuntimen nĂ€ytteistystaajuus 768 MHz. Tavoitteena on saavuttaa teoreettinen 55 dB signaalikohinasuhde (SNR).
TĂ€mĂ€ työ keskittyy jatkuva-aikaisen sigma delta -modulaattorin suunnitteluun ja toteutukseen, perustuen diskreettiaikaisen Æ©â-modulaattorin periaatteisiin ja systeemitason simulointiin ja mallitukseen. Jatkuva-aikaisen sigma delta -modulaattorin kertoimien laskentamenetelmĂ€ esitetÀÀn yksityiskohtaisesti, ja vaatimusten tĂ€yttyminen varmistetaan âtop-downâ -suunnitteluperiaatteella. LiitteenĂ€ on kertoimien laskemiseen kĂ€ytetty MATLAB-koodi. Jatkuva-aikaisten sigma delta -modulaattoreiden erityishaasteiden, liian pitkĂ€n silmukkaviiveen ja kellojitterin herkkyyden, voittamiseksi tutkitaan kahta strategiaa, viiveen kompensointipolkua ja FIR takaisinkytkentĂ€ -DA muunninta. Viivekompensointipolkua kĂ€yttĂ€mĂ€llĂ€ modulaattorin stabiilisuus ja kohinansuodatusfunktio saadaan varmistettua ja korjattua. LisĂ€ksi FIR takaisinkytkentĂ€ -DA-muuntimen kĂ€yttö pienentÀÀ kellojitteriherkkyyttĂ€, parantaen jatkuva aikaisen sigma delta -modulaattorin kokonaissuorituskykyĂ€ ja luotettavuutta.
Toteutetuissa jatkuva-aikaisissa sigma delta -modulaattoreissa on kytketty perÀkkÀin integraattoreita myötÀkytkentÀrakenteella (CIFF) ja toisessa sekÀ myötÀ- ettÀ takaisinkytkentÀrakenteella (CIFF-B). PÀÀhuomio on CIFF-B rakenteessa, joka toteutetaan 22nm CMOS prosessissa kÀyttÀen 0.8 voltin kÀyttöjÀnnitettÀ. Suorityskyky varmistetaan erilaisilla simuloinneilla, joiden perusteella 55 dB SNR saavutetaan 1.36 mW tehonkulutuksella. LisÀksi kohinanmuokkausfunktion optimoinnilla SNR saadaan nostettua 62 desibeliin
Design of a 14-bit fully differential discrete time delta-sigma modulator
Analog to digital converters play an essential role in modern mixed signal circuit design. Conventional Nyquist-rate converters require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can be implemented using simple and high-tolerance analog components. Moreover, sampling at high frequency eliminates the need for abrupt cutoffs in the analog anti-aliasing filters. A noise shaping technique is also used in DS converters in addition to oversampling to achieve a high resolution conversion. A significant advantage of the method is that analog signals are converted using simple and high-tolerance analog circuits, usually a 1-bit comparator, and analog signal processing circuits having a precision that is usually much less than the resolution of the overall converter. In this thesis, a technique to design the discrete time DS converters for 25 kHz baseband signal bandwidth will be described. The noise shaping is achieved using a switched capacitor low-pass integrator around the 1-bit quantizer loop. A latched-type comparator is used as the quantizer of the DS converter. A second order DS modulator is implemented in a TSMC 0.35 Ôm CMOS technology using a 3.3 V power supply. The peak signal-to-noise ratio (SNR) simulated is 87 dB; the SNDR simulated is 82 dB which corresponds to a resolution of 14 bits. The total static power dissipation is 6.6 mW
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