1,445 research outputs found

    A high speed oscillator-based truly random number source for cryptographic applications on a Smart Card IC

    Get PDF
    Special Issue on Cryptographic Hardware and Embedded System

    Testing of PLL-based True Random Number Generator in Changing Working Conditions

    Get PDF
    Security of cryptographic systems depends significantly on security of secret keys. Unpredictability of the keys is achieved by their generation by True Random Number Generators (TRNGs). In the paper we analyze behavior of the Phase-Locked Loop (PLL) based TRNG in changing working environment. The frequency of signals synthesized by PLL may be naturally influenced by chip temperature. We show what impact the temperature has on the quality of generated random sequence of the PLL-based TRNG. Thank to analysis of internal signals of the generator we are able to prove dependencies between the PLL parameters, statistical parameters of the generated sequence and temperature. Considering the measured results of experiments we form a new requirement in order to improve the robustness of the designed TRNG

    On the assumption of mutual independence of jitter realizations in P-TRNG stochastic models

    No full text
    International audienceSecurity in true random number generation in cryptography is based on entropy per bit at the generator output. The entropy is evaluated using stochastic models. Several recent works propose stochastic models based on assumptions related to selected physical analog phenomena such as noise or jittery signal and on the knowledge of the principle of randomness extraction from the obtained analog signal. However, these assumptions simplify often considerably the underlying analog processes, which include several noise sources. In this paper, we present a new comprehensive multilevel approach, which enables to build the stochastic model based on detailed analysis of noise sources starting at transistor level and on conversion of the noise to the clock jitter exploited at the generator level. Using this approach, we can estimate proportion of the jitter coming only from the thermal noise, which is included in the total clock jitter

    D2.1 - Report on Selected TRNG and PUF Principles

    Get PDF
    This report represents the final version of Deliverable 2.1 of the HECTOR work package WP2. It is a result of discussions and work on Task 2.1 of all HECTOR partners involved in WP2. The aim of the Deliverable 2.1 is to select principles of random number generators (RNGs) and physical unclonable functions (PUFs) that fulfill strict technology, design and security criteria. For example, the selected RNGs must be suitable for implementation in logic devices according to the German AIS20/31 standard. Correspondingly, the selected PUFs must be suitable for applying similar security approach. A standard PUF evaluation approach does not exist, yet, but it should be proposed in the framework of the project. Selected RNGs and PUFs should be then thoroughly evaluated from the point of view of security and the most suitable principles should be implemented in logic devices, such as Field Programmable Logic Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) during the next phases of the project

    A Self-timed Ring Based True Random Number Generator

    No full text
    International audienceSelf-timed rings are oscillators in which several events can evolve evenly-spaced in time thanks to analog effects inherent to the ring stage structure. One of their interesting features is that they provide precise high-speed multiphase signals. This paper presents a true random number generator that exploits the jitter of events propagating in a self-timed ring with a high entropy. Designs implemented in Altera Cyclone III and Xilinx Virtex 5 devices provide high quality random bit sequences passing FIPS 140-1 and NIST SP 800-22 statistical tests at a high bit rate

    On Entropy and Bit Patterns of Ring Oscillator Jitter

    Get PDF
    Thermal jitter (phase noise) from a free-running ring oscillator is a common, easily implementable physical randomness source in True Random Number Generators (TRNGs). We show how to evaluate entropy, autocorrelation, and bit pattern distributions of ring oscillator noise sources, even with low jitter levels or some bias. Entropy justification is required in NIST 800-90B and AIS-31 testing and for applications such as the RISC-V entropy source extension. Our numerical evaluation algorithms outperform Monte Carlo simulations in speed and accuracy. We also propose a new lower bound estimation formula for the entropy of ring oscillator sources which applies more generally than previous ones.Comment: 6 page

    Limitations of a True Random Number Generator in a Field Programmable Gate Array

    Get PDF
    Random number generators are used in many areas of engineering, computer science, most notably in simulations and cryptographic applications. There are true random number generators (TRNG) and pseudo random number generators (PRNG). Only a true random number generator is secure because the output bits are non-repeating and nonreproducible. As society has become more dependent on electronic technology the need for true random number generators has increased due to processes that require encryption in everyday use. A fast true random number generator on a field programmable gate array presents digital designers with the ability to have the generator on chip. Since random bits do not have to be brought into the processes from an outside source, they cannot be compromised. An oscillator sampling technique has proved to be an effective TRNG in a Xilinx FPGA. This research examines how the time of the differences in period of the two oscillators, the size of the jitter zone, and whether sampling on the rising and falling edge of the oscillator rather than just the rising edge affects the randomness of the TRNG. The proportion of the size of the jitter zone compared to the period difference between the two oscillators limits the performance of this technique. As the jitter zone gets larger, the proportion of the jitter zone to the difference in periods of the oscillators must increase for the output to remain random. Increasing the output rate by sampling on the rising and falling edge instead of only the rising was not effective. The output was random for only a jitter zone of 24 ps with a period difference of 50 ps and 100 ps

    Delay Measurements and Self Characterisation on FPGAs

    No full text
    This thesis examines new timing measurement methods for self delay characterisation of Field-Programmable Gate Arrays (FPGAs) components and delay measurement of complex circuits on FPGAs. Two novel measurement techniques based on analysis of a circuit's output failure rate and transition probability is proposed for accurate, precise and efficient measurement of propagation delays. The transition probability based method is especially attractive, since it requires no modifications in the circuit-under-test and requires little hardware resources, making it an ideal method for physical delay analysis of FPGA circuits. The relentless advancements in process technology has led to smaller and denser transistors in integrated circuits. While FPGA users benefit from this in terms of increased hardware resources for more complex designs, the actual productivity with FPGA in terms of timing performance (operating frequency, latency and throughput) has lagged behind the potential improvements from the improved technology due to delay variability in FPGA components and the inaccuracy of timing models used in FPGA timing analysis. The ability to measure delay of any arbitrary circuit on FPGA offers many opportunities for on-chip characterisation and physical timing analysis, allowing delay variability to be accurately tracked and variation-aware optimisations to be developed, reducing the productivity gap observed in today's FPGA designs. The measurement techniques are developed into complete self measurement and characterisation platforms in this thesis, demonstrating their practical uses in actual FPGA hardware for cross-chip delay characterisation and accurate delay measurement of both complex combinatorial and sequential circuits, further reinforcing their positions in solving the delay variability problem in FPGAs
    corecore