Bit-Interleaved Coded Modulation Revisited: A Mismatched Decoding Perspective

We revisit the information-theoretic analysis of bit-interleaved coded modulation (BICM) by modeling the BICM decoder as a mismatched decoder. The mismatched decoding model is well-defined for finite, yet arbitrary, block lengths, and naturally captures the channel memory among the bits belonging to the same symbol. We give two independent proofs of the achievability of the BICM capacity calculated by Caire et al. where BICM was modeled as a set of independent parallel binary-input channels whose output is the bitwise log-likelihood ratio. Our first achievability proof uses typical sequences, and shows that due to the random coding construction, the interleaver is not required. The second proof is based on the random coding error exponents with mismatched decoding, where the largest achievable rate is the generalized mutual information. We show that the generalized mutual information of the mismatched decoder coincides with the infinite-interleaver BICM capacity. We also show that the error exponent -and hence the cutoff rate- of the BICM mismatched decoder is upper bounded by that of coded modulation and may thus be lower than in the infinite-interleaved model. We also consider the mutual information appearing in the analysis of iterative decoding of BICM with EXIT charts. We show that the corresponding symbol metric has knowledge of the transmitted symbol and the EXIT mutual information admits a representation as a pseudo-generalized mutual information, which is in general not achievable. A different symbol decoding metric, for which the extrinsic side information refers to the hypothesized symbol, induces a generalized mutual information lower than the coded modulation capacity.Comment: submitted to the IEEE Transactions on Information Theory. Conference version in 2008 IEEE International Symposium on Information Theory, Toronto, Canada, July 200

The Binary Energy Harvesting Channel with a Unit-Sized Battery

We consider a binary energy harvesting communication channel with a finite-sized battery at the transmitter. In this model, the channel input is constrained by the available energy at each channel use, which is driven by an external energy harvesting process, the size of the battery, and the previous channel inputs. We consider an abstraction where energy is harvested in binary units and stored in a battery with the capacity of a single unit, and the channel inputs are binary. Viewing the available energy in the battery as a state, this is a state-dependent channel with input-dependent states, memory in the states, and causal state information available at the transmitter only. We find an equivalent representation for this channel based on the timings of the symbols, and determine the capacity of the resulting equivalent timing channel via an auxiliary random variable. We give achievable rates based on certain selections of this auxiliary random variable which resemble lattice coding for the timing channel. We develop upper bounds for the capacity by using a genie-aided method, and also by quantifying the leakage of the state information to the receiver. We show that the proposed achievable rates are asymptotically capacity achieving for small energy harvesting rates. We extend the results to the case of ternary channel inputs. Our achievable rates give the capacity of the binary channel within 0.03 bits/channel use, the ternary channel within 0.05 bits/channel use, and outperform basic Shannon strategies that only consider instantaneous battery states, for all parameter values.Comment: Submitted to IEEE Transactions on Information Theory, August 201

Channels with block interference

A new class of channel models with memory is presented in order to study various kinds of interference phenomena. It is shown, among other things, that when all other parameters are held fixed, channel capacity C is an increasing function of the memory length, while the cutoff rate R0 generally is a decreasing function. Calculations with various explicit coding schemes indicate that C is better than R0 as a performance measure for these channel models. As a partial resolution of this C versus R0 paradox, the conjecture is offered that R0 is more properly a measure of coding delay rather than of coding complexity

Write Channel Model for Bit-Patterned Media Recording

We propose a new write channel model for bit-patterned media recording that reflects the data dependence of write synchronization errors. It is shown that this model accommodates both substitution-like errors and insertion-deletion errors whose statistics are determined by an underlying channel state process. We study information theoretic properties of the write channel model, including the capacity, symmetric information rate, Markov-1 rate and the zero-error capacity.Comment: 11 pages, 12 figures, journa

YodaNN: An Architecture for Ultra-Low Power Binary-Weight CNN Acceleration

Convolutional neural networks (CNNs) have revolutionized the world of computer vision over the last few years, pushing image classification beyond human accuracy. The computational effort of today's CNNs requires power-hungry parallel processors or GP-GPUs. Recent developments in CNN accelerators for system-on-chip integration have reduced energy consumption significantly. Unfortunately, even these highly optimized devices are above the power envelope imposed by mobile and deeply embedded applications and face hard limitations caused by CNN weight I/O and storage. This prevents the adoption of CNNs in future ultra-low power Internet of Things end-nodes for near-sensor analytics. Recent algorithmic and theoretical advancements enable competitive classification accuracy even when limiting CNNs to binary (+1/-1) weights during training. These new findings bring major optimization opportunities in the arithmetic core by removing the need for expensive multiplications, as well as reducing I/O bandwidth and storage. In this work, we present an accelerator optimized for binary-weight CNNs that achieves 1510 GOp/s at 1.2 V on a core area of only 1.33 MGE (Million Gate Equivalent) or 0.19 mm$^2$ and with a power dissipation of 895 {\mu}W in UMC 65 nm technology at 0.6 V. Our accelerator significantly outperforms the state-of-the-art in terms of energy and area efficiency achieving 61.2 TOp/s/[email protected] V and 1135 GOp/s/[email protected] V, respectively