Evaluation des performances des mémoires CBRAM (Conductive bridge memory) afin d’optimiser les empilements technologiques et les solutions d’intégration

The constant evolution of the data storage needs over the last decades have led the technological landscape to completely change and reinvent itself. From the early stage of magnetic storage to the most recent solid state devices, the bit density keeps increasing toward what seems from a consumer point of view infinite storage capacity and performances. However, behind each storage technology transition stand density and performances limitations that required strong research work to overcome. This manuscript revolves around one of the promising emerging technology aiming to revolutionize data storage landscape: the Conductive Bridge Random Access Memory (CBRAM). This technology based on the reversible formation and dissolution of a conductive path in a solid electrolyte matrix offers great advantages in term of power consumption, performances, density and the possibility to be integrated in the back end of line. However, for this technology to be competitive some roadblocks still have to be overcome especially regarding the technology variability, reliability and thermal stability. This manuscript proposes a comprehensive understanding of the CBRAM operations based on experimental results and a specially developed Kinetic Monte Carlo model. This understanding creates bridges between the physical properties of the materials involved in the devices and the devices performances (Forming, SET and RESET time and voltage, retention, endurance, variability). A strong emphasis is placed on the current limitations of the technology previously stated and how to overcome these limitations. Improvement of the thermal stability and device reliability are demonstrated with optimized operating conditions and proper devices engineering.Ces dernières décennies, la constante évolution des besoins de stockage de données a mené à un bouleversement du paysage technologique qui s’est complètement métamorphosé et réinventé. Depuis les débuts du stockage magnétique jusqu’aux plus récents dispositifs fondés sur l’électronique dit d’état solide, la densité de bits stockés continue d’augmenter vers ce qui semble du point de vue du consommateur comme des capacités de stockage et des performances infinies. Cependant, derrière chaque transition et évolution des technologies de stockage se cachent des limitations en termes de densité et performances qui nécessitent de lourds travaux de recherche afin d’être surmontées et repoussées. Ce manuscrit s’articule autour d’une technologie émergeante prometteuse ayant pour vocation de révolutionner le paysage du stockage de données : la mémoire à pont conducteur ou Conductive Bridge Random Access Memory (CBRAM). Cette technologie est fondée sur la formation et dissolution réversible d’un chemin électriquement conducteur dans un électrolyte solide. Elle offre de nombreux avantages face aux technologies actuelles tels qu’une faible consommation électrique, de très bonnes performances d’écriture et de lecture et la capacité d’être intégré aux seins des interconnexions métalliques d’une puce afin d’augmenter la densité de stockage. Malgré tout, pour que cette technologie soit compétitive certaines limitations ont besoin d’être surmontées et particulièrement sa variabilité et sa stabilité thermique qui posent encore problème. Ce manuscrit propose une compréhension physique globale du fonctionnement de la technologie CBRAM fondée sur une étude expérimentale approfondie couplée à un modèle Monte Carlo cinétique spécialement développé. Cette compréhension fait le lien entre les propriétés physiques des matériaux composant la mémoire CBRAM et ses performances (Tension et temps d’écriture et d’effacement, rétention de donnée, endurance et variabilité). Un fort accent est mis la compréhension des limites actuelle de la technologie et comment les repousser. Grâce à une optimisation des conditions d’opérations ainsi qu’à un travail d’ingénierie des dispositifs mémoire, il est démontré dans ce manuscrit une forte amélioration de la stabilité thermique ainsi que de la variabilité des états écrits et effacés

Nouvelles Architectures Hybrides (Logique / Mémoires Non-Volatiles et technologies associées.)

Les nouvelles approches de technologies mémoires permettront une intégration dite back-end, où les cellules élémentaires de stockage seront fabriquées lors des dernières étapes de réalisation à grande échelle du circuit. Ces approches innovantes sont souvent basées sur l'utilisation de matériaux actifs présentant deux états de résistance distincts. Le passage d'un état à l'autre est contrôlé en courant ou en tension donnant lieu à une caractéristique I-V hystérétique. Nos mémoires résistives sont composées d'argent en métal électrochimiquement actif et de sulfure amorphe agissant comme électrolyte. Leur fonctionnement repose sur la formation réversible et la dissolution d'un filament conducteur. Le potentiel d'application de ces nouveaux dispositifs n'est pas limité aux mémoires ultra-haute densité mais aussi aux circuits embarqués. En empilant ces mémoires dans la troisième dimension au niveau des interconnections des circuits logiques CMOS, de nouvelles architectures hybrides et innovantes deviennent possibles. Il serait alors envisageable d'exploiter un fonctionnement à basse énergie, à haute vitesse d'écriture/lecture et de haute performance telles que l'endurance et la rétention. Dans cette thèse, en se concentrant sur les aspects de la technologie de mémoire en vue de développer de nouvelles architectures, l'introduction d'une fonctionnalité non-volatile au niveau logique est démontrée par trois circuits hybrides: commutateurs de routage non volatiles dans un Field Programmable Gate Arrays, un 6T-SRAM non volatile, et les neurones stochastiques pour un réseau neuronal. Pour améliorer les solutions existantes, les limitations de la performances des dispositifs mémoires sont identifiés et résolus avec des nouveaux empilements ou en fournissant des défauts de circuits tolérants.Novel approaches in the field of memory technology should enable backend integration, where individual storage nodes will be fabricated during the last fabrication steps of the VLSI circuit. In this case, memory operation is often based upon the use of active materials with resistive switching properties. A topology of resistive memory consists of silver as electrochemically active metal and amorphous sulfide acting as electrolyte and relies on the reversible formation and dissolution of a conductive filament. The application potential of these new memories is not limited to stand-alone (ultra-high density), but is also suitable for embedded applications. By stacking these memories in the third dimension at the interconnection level of CMOS logic, new ultra-scalable hybrid architectures becomes possible which exploit low energy operation, fast write/read access and high performance with respect to endurance and retention. In this thesis, focusing on memory technology aspects in view of developing new architectures, the introduction of non-volatile functionality at the logic level is demonstrated through three hybrid (CMOS logic ReRAM devices) circuits: nonvolatile routing switches in a Field Programmable Gate Array, nonvolatile 6T-SRAMs, and stochastic neurons of an hardware neural network. To be competitive or even improve existing solutions, limitations on the memory devices performances are identified and solved by stack engineering of CBRAM devices or providing faults tolerant circuits.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Standards for the Characterization of Endurance in Resistive Switching Devices

Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to variability and reliability issues, which are usually evaluated through switching endurance tests. However, we note that most studies that claimed high endurances >106 cycles were based on resistance versus cycle plots that contain very few data points (in many cases even <20), and which are collected in only one device. We recommend not to use such a characterization method because it is highly inaccurate and unreliable (i.e., it cannot reliably demonstrate that the device effectively switches in every cycle and it ignores cycle-to-cycle and device-to-device variability). This has created a blurry vision of the real performance of RS devices and in many cases has exaggerated their potential. This article proposes and describes a method for the correct characterization of switching endurance in RS devices; this method aims to construct endurance plots showing one data point per cycle and resistive state and combine data from multiple devices. Adopting this recommended method should result in more reliable literature in the field of RS technologies, which should accelerate their integration in commercial products

Design of Neuromemristive Systems for Visual Information Processing

Neuromemristive systems (NMSs) are brain-inspired, adaptive computer architectures based on emerging resistive memory technology (memristors). NMSs adopt a mixed-signal design approach with closely-coupled memory and processing, resulting in high area and energy efficiencies. Previous work suggests that NMSs could even supplant conventional architectures in niche application domains such as visual information processing. However, given the infancy of the field, there are still several obstacles impeding the transition of these systems from theory to practice. This dissertation advances the state of NMS research by addressing open design problems spanning circuit, architecture, and system levels. Novel synapse, neuron, and plasticity circuits are designed to reduce NMSs’ area and power consumption by using current-mode design techniques and exploiting device variability. Circuits are designed in a 45 nm CMOS process with memristor models based on multilevel (W/Ag-chalcogenide/W) and bistable (Ag/GeS2/W) device data. Higher-level behavioral, power, area, and variability models are ported into MATLAB to accelerate the overall simulation time. The circuits designed in this work are integrated into neural network architectures for visual information processing tasks, including feature detection, clustering, and classification. Networks in the NMSs are trained with novel stochastic learning algorithms that achieve 3.5 reduction in circuit area, reduced design complexity, and exhibit similar convergence properties compared to the least-mean-squares algorithm. This work also examines the effects of device-level variations on NMS performance, which has received limited attention in previous work. The impact of device variations is reduced with a partial on-chip training methodology that enables NMSs to be configured with relatively sophisticated algorithms (e.g. resilient backpropagation), while maximizing their area-accuracy tradeoff

Quantum Conductance in Memristive Devices: Fundamentals, Developments, and Applications

Quantum effects in novel functional materials and new device concepts represent a potential breakthrough for the development of new information processing technologies based on quantum phenomena. Among the emerging technologies, memristive elements that exhibit resistive switching, which relies on the electrochemical formation/rupture of conductive nanofilaments, exhibit quantum conductance effects at room temperature. Despite the underlying resistive switching mechanism having been exploited for the realization of next-generation memories and neuromorphic computing architectures, the potentialities of quantum effects in memristive devices are still rather unexplored. Here, a comprehensive review on memristive quantum devices, where quantum conductance effects can be observed by coupling ionics with electronics, is presented. Fundamental electrochemical and physicochemical phenomena underlying device functionalities are introduced, together with fundamentals of electronic ballistic conduction transport in nanofilaments. Quantum conductance effects including quantum mode splitting, stability, and random telegraph noise are analyzed, reporting experimental techniques and challenges of nanoscale metrology for the characterization of memristive phenomena. Finally, potential applications and future perspectives are envisioned, discussing how memristive devices with controllable atomic-sized conductive filaments can represent not only suitable platforms for the investigation of quantum phenomena but also promising building blocks for the realization of integrated quantum systems working in air at room temperature.status: publishe

Solution-processed stretchable Ag2S semiconductor thin films for wearable self-powered nonvolatile memory

Department of Materials Science and EngineeringStretchable thin films have facilitated the developments in the field of flexible and stretchable electronics such as deformable sensors, displays, memories and energy devices which have received significant attention due to their potential use in smart wearable devices. Potential candidates for stretchable materials include polymer-based elastomers and their composites with functional fillers but they intrinsically suffer from low electrical properties. Compared to large plastic deformations observed in elastomeric organic materials, inorganic semiconductors have low plasticity (< 0.2%) due to their unique bonding properties which restrict applications in stretchable electronics. ??-Ag2S bulk crystals, a member of the metal chalcogenide, is considered as a promising candidate to produce deformable semiconductor layers in flexible and stretchable electronics due to its outstanding mechanical and electrical properties. An extremely low slippage energy and high cleavage energy between the crystal planes of ??-Ag2S bulk crystals exhibit both semiconducting behavior and ductility similar to metals. Such unusual characteristics have abundant potential for energy and electronic applications. Although several studies reported the use of Ag2S bulk ingots in energy devices, the fabrication of Ag2S thin films based stretchable electronics have never been realized due to highly complicated synthetic procedures. Typical procedures for producing ??-Ag2S crystals require energy intensive process, such as SPS sintering method and complicated deposition equipment set-up, limiting both the available substrates and processing temperatures for the fabrication of flexible and stretchable electronics. The solution process of metal chalcogenides thin films has been of great interest since it provides the ability to fabricate high quality and scalable thin films in a low-cost manner. Recent discoveries of alkahest solvent, a mixture of amine and thiol solutions allowed soluble inorganic to be utilized as ink processing for thin films. Furthermore, the metal chalcogenide inks can achieve highly crystalline and uniform thin films using a simple solution process and a subsequent heat treatment. I herein report solution-process synthesis of ductile ??-Ag2S thin films and the manufacturing process of all inorganic, self-powered and stretchable memory devices. The molecular Ag2S complex solution was synthesized by chemical reduction of bulk Ag2S powder to produce a wafer-scale, highly crystalline Ag2S thin film. Thin films exhibit elasticity through inherent ductility and maintain structural integrity with 14.9 % tensile strain. In addition, Ag2S-based resistive memory manufactured has excellent bipolar switching characteristics (Ion/Ioff ratio of ~105, operational endurance of 100 cycles, and retention time > 106 s) and excellent mechanical elasticity (no degradation to elasticity). On the other hand, the device is very durable in a variety of chemical environments and temperatures between -196 and 300 ??C, especially at 85% relative humidity and 85 ??C for 168 hours. Finally, I demonstrate self-powered memory device combined with motion sensors for a wearable health monitoring system, which potentially offers to design high-performance wearable electronics for everyday use in real-world environments.ope

Etude des cellules mémoires résistives RRAM à base de HfO2 par caractérisation électrique et simulations atomistiques

Among non-volatile memory technologies, NAND Flash represents a significant portion in the IC market and has benefitted from the traditional scaling of semiconductor industry allowing its high density integration. However, this scaling seems to be problematic beyond the 22 nm node. In an effort to go beyond this scaling limitation, alternative memory solutions are proposed among which Resistive RAM (RRAM) stands out as a serious candidate for NAND Flash replacement. Hence, in this PhD thesis we try to respond to many open questions about RRAM devices based on hafnium oxide (HfO2), in particular, by addressing the lack of detailed physical comprehension about their operation and reliability. The impact of scaling, the role of electrodes, the process of defects formation and diffusion are investigated. The impact of alloying/doping HfO2 with other materials for improved RRAM performance is also studied. Finally, our study attempts to provide some answers on the conductive filament formation, its stability and possible composition.La mémoire NAND Flash représente une part importante dans le marché des circuits intégrés et a bénéficié de la traditionnelle miniaturisation de l’industrie des sémiconducteurs lui permettant un niveau d’intégration élevé. Toutefois, cette miniaturisation semble poser des sérieux problèmes au-delà du noeud 22 nm. Dans un souci de dépasser cette limite, des solutions mémoires alternatives sont proposées parmi lesquelles la mémoire résistive (RRAM) se pose comme un sérieux candidat pour le remplacement de NAND Flash. Ainsi, dans cette thèse nous essayons de répondre à des nombreuses questions ouvertes sur les dispositifs RRAM à base d’oxyde d’hafnium (HfO2) en particulier en adressant le manque de compréhension physique détaillée sur leur fonctionnement et leur fiabilité. L’impact de la réduction de taille des RRAM, le rôle des électrodes et le processus de formation et de diffusion des défauts sont étudiés. L’impact de l’alliage/dopage de HfO2 avec d’autres matériaux pour l’optimisation des RRAM est aussi abordé. Enfin, notre étude tente de donner quelques réponses sur la formation du filament conducteur, sa stabilité et sa possible composition

Inertness and Other Properties of Thin Ruthenium Electrodes in ReRAM Applications

Building nonvolatile memory such as resistive random access memory (ReRAM) directly into a CMOS backend (BEOL) would reduce latency in connectivity-constrained devices and reduce chip’s footprint by stacking non-volatile memory (NVM) on top of the logic circuits. This co-integration is facilitated by a broad commonality between ReRAM and BEOL as both rely on the same basic metal–insulator–metal (MIM) structure. One good candidate for a ReRAM cell is the Cu/TaOx/Pt device. As platinum (Pt) is not an economic choice, a BEOL-compatible replacement is desirable. A good candidate to replace Pt electrode is ruthenium (Ru), currently being used as a liner/diffusion barrier in sub-15 nm technology nodes and soon to supplant tungsten as via, and copper (Cu) as interconnect materials. We report on extensive characterization of a Cu/TaOx/Ru device and compare its performance and reliability with extant ReRAM devices. Against the background of well-characterized non-Ru ReRAM devices, Cu/TaOx/Ru cell constitutes a micro-laboratory for testing a wide range of Ru properties with the Cu nanofilament as a probe. Since the temperature of the cell can be controlled internally from 27°C to ∼1100°C, thin Ru layers can be subjected to much more comprehensive tests than it is possible in the interconnect MIM structures and reveal and confirm interesting material properties, including the impact of embedment

Caractérisation et conception d' architectures basées sur des mémoires à changement de phase

Semiconductor memory has always been an indispensable component of modern electronic systems. The increasing demand for highly scaled memory devices has led to the development of reliable non-volatile memories that are used in computing systems for permanent data storage and are capable of achieving high data rates, with the same or lower power dissipation levels as those of current advanced memory solutions.Among the emerging non-volatile memory technologies, Phase Change Memory (PCM) is the most promising candidate to replace conventional Flash memory technology. PCM offers a wide variety of features, such as fast read and write access, excellent scalability potential, baseline CMOS compatibility and exceptional high-temperature data retention and endurance performances, and can therefore pave the way for applications not only in memory devices, but also in energy demanding, high-performance computer systems. However, some reliability issues still need to be addressed in order for PCM to establish itself as a competitive Flash memory replacement.This work focuses on the study of embedded Phase Change Memory in order to optimize device performance and propose solutions to overcome the key bottlenecks of the technology, targeting high-temperature applications. In order to enhance the reliability of the technology, the stoichiometry of the phase change material was appropriately engineered and dopants were added, resulting in an optimized thermal stability of the device. A decrease in the programming speed of the memory technology was also reported, along with a residual resistivity drift of the low resistance state towards higher resistance values over time.A novel programming technique was introduced, thanks to which the programming speed of the devices was improved and, at the same time, the resistance drift phenomenon could be successfully addressed. Moreover, an algorithm for programming PCM devices to multiple bits per cell using a single-pulse procedure was also presented. A pulse generator dedicated to provide the desired voltage pulses at its output was designed and experimentally tested, fitting the programming demands of a wide variety of materials under study and enabling accurate programming targeting the performance optimization of the technology.Les mémoires à base de semi-conducteur sont indispensables pour les dispositifs électroniques actuels. La demande croissante pour des dispositifs mémoires fortement miniaturisées a entraîné le développement de mémoires non volatiles fiables qui sont utilisées dans des systèmes informatiques pour le stockage de données et qui sont capables d'atteindre des débits de données élevés, avec des niveaux de dissipation d'énergie équivalents voire moindres que ceux des technologies mémoires actuelles.Parmi les technologies de mémoires non-volatiles émergentes, les mémoires à changement de phase (PCM) sont le candidat le plus prometteur pour remplacer la technologie de mémoire Flash conventionnelle. Les PCM offrent une grande variété de fonctions, comme une lecture et une écriture rapide, un excellent potentiel de miniaturisation, une compatibilité CMOS et des performances élevées de rétention de données à haute température et d'endurance, et peuvent donc ouvrir la voie à des applications non seulement pour les dispositifs mémoires, mais également pour les systèmes informatiques à hautes performances. Cependant, certains problèmes de fiabilité doivent encore être résolus pour que les PCM se positionnent comme un remplacement concurrentiel de la mémoire Flash.Ce travail se concentre sur l'étude de mémoires à changement de phase intégrées afin d'optimiser leurs performances et de proposer des solutions pour surmonter les principaux points critiques de la technologie, ciblant des applications à hautes températures. Afin d'améliorer la fiabilité de la technologie, la stœchiométrie du matériau à changement de phase a été conçue de façon appropriée et des dopants ont été ajoutés, optimisant ainsi la stabilité thermique. Une diminution de la vitesse de programmation est également rapportée, ainsi qu'un drift résiduel de la résistance de l'état de faiblement résistif vers des valeurs de résistance plus élevées au cours du temps.Une nouvelle technique de programmation est introduite, permettant d'améliorer la vitesse de programmation des dispositifs et, dans le même temps, de réduire avec succès le phénomène de drift en résistance. Par ailleurs, un algorithme de programmation des PCM multi-bits est présenté. Un générateur d'impulsions fournissant des impulsions avec la tension souhaitée en sortie a été conçu et testé expérimentalement, répondant aux demandes de programmation d'une grande variété de matériaux innovants et en permettant la programmation précise et l’optimisation des performances des PCM