SIRU development. Volume 1: System development

A complete description of the development and initial evaluation of the Strapdown Inertial Reference Unit (SIRU) system is reported. System development documents the system mechanization with the analytic formulation for fault detection and isolation processing structure; the hardware redundancy design and the individual modularity features; the computational structure and facilities; and the initial subsystem evaluation results

Multifunction tests of a frequency domain based flutter suppression system

The process is described of analysis, design, digital implementation, and subsonic testing of an active control flutter suppression system for a full span, free-to-roll wind tunnel model of an advanced fighter concept. The design technique uses a frequency domain representation of the plant and used optimization techniques to generate a robust multi input/multi output controller. During testing in a fixed-in-roll configuration, simultaneous suppression of both symmetric and antisymmetric flutter was successfully shown. For a free-to-roll configuration, symmetric flutter was suppressed to the limit of the tunnel test envelope. During aggressive rolling maneuvers above the open-loop flutter boundary, simultaneous flutter suppression and maneuver load control were demonstrated. Finally, the flutter damping controller was reoptimized overnight during the test using combined experimental and analytical frequency domain data, resulting in improved stability robustness

High-resolution width-modulated pulse rebalance electronics for strapdown gyroscopes and accelerometers

Three different rebalance electronic loops were designed, implemented, and evaluated. The loops were width-modulated binary types using a 614.4 kHz keying signal; they were developed to accommodate the following three inertial sensors with the indicated resolution values: (1) Kearfott 2412 accelerometer - resolution = 260 micro-g/data pulse, (2) Honeywell GG334 gyroscope - resolution = 3.9 milli-arc-sec/data pulse, (3) Kearfott 2401-009 accelerometer - resolution = 144 milli-g/data pulse. Design theory, details of the design implementation, and experimental results for each loop are presented

Digital Pulse Width Modulator Techniques For Dc - Dc Converters

Recent research activities focused on improving the steady-state as well as the dynamic behavior of DC-DC converters for proper system performance, by proposing different design methods and control approaches with growing tendency to using digital implementation over analog practices. Because of the rapid advancement in semiconductors and microprocessor industry, digital control grew in popularity among PWM converters and is taking over analog techniques due to availability of fast speed microprocessors, flexibility and immunity to noise and environmental variations. Furthermore, increased interest in Field Programmable Gate Arrays (FPGA) makes it a convenient design platform for digitally controlled converters. The objective of this research is to propose new digital control schemes, aiming to improve the steady-state and transient responses of a high switching frequency FPGA-based digitally controlled DC-DC converters. The target is to achieve enhanced performance in terms of tight regulation with minimum power consumption and high efficiency at steady-state, as well as shorter settling time with optimal over- and undershoots during transients. The main task is to develop new and innovative digital PWM techniques in order to achieve: 1. Tight regulation at steady-state: by proposing high resolution DPWM architecture, based on Digital Clock Management (DCM) resources available on FPGA boards. The proposed architecture Window-Masked Segmented Digital Clock Manager-FPGA based Digital Pulse Width Modulator Technique, is designed to achieve high resolution operating at high switching frequencies with minimum power consumption. 2. Enhanced dynamic response: by applying a shift to the basic saw-tooth DPWM signal, in order to benefit from the best linearity and simplest architecture offered by the conventional counter-comparator DPWM. This proposed control scheme will help the compensator reach the steady-state value faster. Dynamically Shifted Ramp Digital Control Technique for Improved Transient Response in DC-DC Converters, is projected to enhance the transient response by dynamically controlling the ramp signal of the DPWM unit

Quantization noise analysis of a closed-loop PWM controller that includes Σ-Δ modulation

Σ-Δ modulation is a popular noise shaping technique which is used to move the quantization noise out of the frequency band of interest. Recently, a number of authors have applied this technique to a pulse width modulation (PWM) controller for switching power converters. However, previous analysis has not incorporated the effects of analog-to-digital converter (ADC) resolution or feedback control on the Σ-Δ modulator. In this work, quantization due to ADC resolution and PWM resolution are analyzed, considering the effects of noise-shaping and feedback. A number of simulations have been performed to explore the impact of various design choices on output noise. The study variables included the order of the Σ-Δ modulator, resolution of ADC, resolution of DPWM, the plant and the compensator. The theoretical model developed is used to generate the expected system Power Spectral Density (PSD) curves for each design choice and simulations techniques are used to validate the analysis. Experimental analysis has been performed on a digital voltage-mode control (VMC) synchronous buck converter and the output voltage PSD curves are generated using the welch method and compared with the theoretical and the simulation results. The experimental PSD curves for the 1st-order modulator match the simulation and theoretical PSD curves. This suggests that the theoretical model is a useful approximation and similar methods can be used to analyze the contribution of the quantizers to the output noise of a closed-loop controller system --Abstract, page iii

A Two-stage approach to harmonic rejection mixing using blind interference cancelling

Current analog harmonic rejection mixers typically provide 30–40 dB of harmonic rejection, which is often not sufficient. We present a mixed analog-digital approach to harmonic rejection mixing that uses a digital interference canceler to reject the strongest interferer. Simulations indicate that, given a practical RF scenario, the digital canceler is able to improve the signal-to-interference ratio by 30–45 dB

Design, test, and evaluation of three active flutter suppression controllers

Three control law design techniques for flutter suppression are presented. Each technique uses multiple control surfaces and/or sensors. The first method uses traditional tools (such as pole/zero loci and Nyquist diagrams) for producing a controller that has minimal complexity and which is sufficiently robust to handle plant uncertainty. The second procedure uses linear combinations of several accelerometer signals and dynamic compensation to synthesize the model rate of the critical mode for feedback to the distributed control surfaces. The third technique starts with a minimum-energy linear quadratic Gaussian controller, iteratively modifies intensity matrices corresponding to input and output noise, and applies controller order reduction to achieve a low-order, robust controller. The resulting designs were implemented digitally and tested subsonically on the active flexible wing wind-tunnel model in the Langley Transonic Dynamics Tunnel. Only the traditional pole/zero loci design was sufficiently robust to errors in the nominal plant to successfully suppress flutter during the test. The traditional pole/zero loci design provided simultaneous suppression of symmetric and antisymmetric flutter with a 24-percent increase in attainable dynamic pressure. Posttest analyses are shown which illustrate the problems encountered with the other laws

Synthesis and Analysis of Design Methods in Linear Repetitive, Iterative Learning and Model Predictive Control

Repetitive Control (RC) seeks to converge to zero tracking error of a feedback control system performing periodic command as time progresses, or to cancel the influence of a periodic disturbance as time progresses, by observing the error in the previous period. Iterative Learning Control (ILC) is similar, it aims to converge to zero tracking error of system repeatedly performing the same task, and also adjusting the command to the feedback controller each repetition based on the error in the previous repetition. Compared to the conventional feedback control design methods, RC and ILC improve the performance over repetitions, and both aiming at zero tracking error in the real world instead of in a mathematical model. Linear Model Predictive Control (LMPC) normally does not aim for zero tracking error following a desired trajectory, but aims to minimize a quadratic cost function to the prediction horizon, and then apply the first control action. Then repeat the process each time step. The usual quadratic cost is a trade-off function between tracking accuracy and control effort and hence is not asking for zero error. It is also not specialized to periodic command or periodic disturbance as RC is, but does require that one knows the future desired command up to the prediction horizon. The objective of this dissertation is to present various design schemes of improving the tracking performance in a control system based on ILC, RC and LMPC. The dissertation contains four major chapters. The first chapter studies the optimization of the design parameters, in particular as related to measurement noise, and the need of a cutoff filter when dealing with actuator limitations, robustness to model error. The results aim to guide the user in tuning the design parameters available when creating a repetitive control system. In the second chapter, we investigate how ILC laws can be converted for use in RC to improve performance. And robustification by adding control penalty in cost function is compared to use a frequency cutoff filter. The third chapter develops a method to create desired trajectories with a zero tracking interval without involving an unstable inverse solution. An easily implementable feedback version is created to optimize the same cost every time step from the current measured position. An ILC algorithm is also created to iteratively learn to give local zero error in the real world while using an imperfect model. This approach also gives a method to apply ILC to endpoint problem without specifying an arbitrary trajectory to follow to reach the endpoint. This creates a method for ILC to apply to such problems without asking for accurate tracking of a somewhat arbitrary trajectory to accomplish learning to reach the desired endpoint. The last chapter outlines a set of uses for a stable inverse in control applications, including Linear Model Predictive Control (LMPC), and LMPC applied to Repetitive Control (RC-LMPC), and a generalized form of a one-step ahead control. An important characteristic is that this approach has the property of converging to zero tracking error in a small number of time steps, which is finite time convergence instead of asymptotic convergence as time tends to infinity

Sincronização de quadro e frequência para OFDM no padrão IEEE 802.15.4g : algoritmos e implementação em hardware

Orientadores: Renato da Rocha Lopes, Eduardo Rodrigues de LimaDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: O objetivo deste trabalho é propor métodos de sincronização de quadro e de frequência de portadora para a camada física MR-OFDM do padrão IEEE 802.15.4g, começando pela pesquisa de algoritmos, passando pelas etapas de modelagem e simulação em alto nível, e finalmente implementando e avaliando os métodos propostos em hardware. A sincronização de quadro é o processo responsável por detectar o início do dado transmitido, ou seja, a primeira amostra válida do sinal de interesse. No caso de sistemas OFDM, onde o sinal transmitido é composto por um ou mais símbolos OFDM (cada símbolo sendo composto por uma quantidade fixa de amostras), o objetivo é detectar a borda ou janelamento de tais símbolos OFDM, ou seja, onde começa e termina cada um deles. A sincronização de frequência, por sua vez, consiste em estimar e compensar o erro de frequência de portadora, causado principalmente pelo descasamento dos osciladores do transmissor e do receptor. Com base em estudos preliminares, selecionamos o algoritmo de Minn para a detecção de quadro. Para a correção de erro de frequência, dividimos o processo em duas etapas, como é geralmente proposto na literatura: primeiro, o erro de frequência fracionário é estimado no domínio do tempo durante a detecção de quadro e compensado via rotação de sinal; após a conversão do domínio do tempo para o domínio da frequência, o erro de frequência inteiro é estimado e compensado utilizando um novo e simples algoritmo que será proposto e detalhado neste trabalho. Os algoritmos propostos foram implementados em hardware e uma plataforma de verificação baseada em FPGA foi criada para avaliar o seu desempenho. Os módulos implementados são parte de um projeto que está sendo desenvolvido no Instituto de Pesquisa Eldorado (Campinas) que tem como objetivo implementar em ASIC um transceptor compatível com o padrão IEEE 802.15.4gAbstract: The objective of this work is proposing methods of frame and frequency synchronization for the MR-OFDM PHY of IEEE 802.15.4g standard, starting with the research of state-of-the-art algorithms, passing through modeling, high-level simulations, and finally implementing and evaluating the proposed methods in hardware. Frame synchronization is the process responsible for detecting the beginning of transmitted data and, in the case of OFDM systems, the border of each OFDM symbol, while frequency synchronization consists of estimating and compensating the Carrier Frequency Offset (CFO) caused mainly by a mismatch between the transmitter and receiver oscillators. Based on the initial studies, we selected Minn¿s algorithm for frame detection. For the CFO correction, we split the process into two steps, as commonly proposed in the literature: first, the Fractional CFO is estimated in the time domain during the frame detection and compensated via signal rotation; after the conversion from time to frequency domain, the Integer CFO is estimated and compensated with a novel and simple algorithm that will be detailed in this work. The proposed algorithms were implemented in hardware and inserted in an FPGA-based verification platform for performance measurement. The implemented modules are part of a project that is under development at Eldorado Research Institute (Campinas) and aims to implement in ASIC a transceiver compliant to the IEEE 802.15.4g standardMestradoTelecomunicações e TelemáticaMestra em Engenharia Elétric