1,522 research outputs found

    A selectable-bandwidth 3.5 mW, 0.03 mm(2) self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth

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    In this paper we present a dual-mode third order continuous time Sigma Delta modulator that combines noise shaping and pulse-width-modulation (PWM). In our 0.18 micro-m CMOS prototype chip the clock frequency equals 1 GHz, but the PWM carrier is only around 125 MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10 MHz. In the 5 MHz mode the peak SNDR equals 64 dB and the dynamic range 71 dB. In the 10 MHz mode the peak SNDR equals 58 dB and the DR 65 dB. This performance is achieved at an attractively low silicon area of 0.03 mm^2 and a power consumption of 3.5 mW

    True high-order VCO-based ADC

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    A novel approach to use a voltage-controlled oscillator (VCO) as the first integrator of a high-order continuous-time delta-sigma modulator (CT-DSM) is presented. In the proposed architecture, the VCO is combined with a digital up-down counter to implement the first integrator of the CT-DSM. Thus, the first integrator is digital-friendly and hence can maximally benefit from technological scaling

    Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits

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    This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs). Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB. The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date

    Multi-band Oversampled Noise Shaping Analog to Digital Conversion

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    Oversampled noise shaping analog to digital (A/D) converters, which are commonly known as delta-sigma (ΔΣ) converters, have the ability to convert relatively low bandwidth signals with very high resolution. Such converters achieve their high resolution by oversampling, as well as processing the signal and quantization noise with different transfer functions. The signal transfer function (STF) is typically a delay over the signal band while the noise transfer function (NTF) is designed to attenuate quantization noise in the signal band. A side effect of the NTF is an amplification of the noise outside the signal band. Thus, a digital filter subsequently attenuates the out-of-band quantization noise. The focus of this thesis is the investigation of ΔΣ architectures that increase the bandwidth where high resolution conversion can be achieved. It uses parallel architectures exploiting frequency or time slicing to meet this objective. Frequency slicing involves quantizing different portions of the signal frequency spectrum using several quantizers in parallel and then combining the results of the quantizers to form an overall result. Time slicing involves quantizing various groups of time domain signal samples with different quantizers in parallel and then combining the results of the quantizers to form an overall output. Several interesting observations can be made from this general perspective of frequency and time slicing. Although the representation of a signal are completely equivalent in time or frequency, the thesis shows that this is not the case for known frequency and time sliced A/D architectures. The performance of such systems under ideal conditions are compared for PCM as well as for ΔΣ A/D converters. A multi-band frequency sliced architecture for delta-sigma conversion is proposed and its performance is included in the above comparison. The architecture uses modulators which realize different NTFs for different portions of the signal band. Each band is converted in parallel. A bank of FIR filters attenuates the out of-band noise for each band and achieves perfect reconstruction of the signal component. A design procedure is provided for the design of the filter bank with reduced computational complexity. The use of complex NTFs in the multi-band ΔΣ architecture is also proposed. The peformance of real and complex NTFs is compared. Performance evaluations are made for ideal systems as well as systems suffering from circuit implementation imperfections such as finite opamp gain and mismatched capacitor ratios

    A novel low-voltage reconfigurable ΣΔ modulator for 4G wireless receivers

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    This paper presents a new adaptable cascade ΣΔ modulator architecture fo r low-voltage multi-stan- dard applications. It uses two reconfiguration strategies: a programmable global resonation and a variable loop-filter order. These techniques are properly com- bined in a novel topology that allows to increase the effec- tive resolution in a given bandwidth, whereas keeping relaxed output swing requirements and high robustness to mismatch and to non-linearities of the amplifiers. Time-domain simulations incl uding the main circuit-level non-idealities are shown to demonstrate the benefits of the presented modulator when it is configured to cope with the requirements of GSM, UMTS, WLAN and Wi-Max.España, Ministerio de Educación y Ciencia TEC2007-67247-C02-01/MICEspaña, Ministerio de Innovación, Ciencia y Empresa, Junta de Andalucía TIC-253

    Comparison of Simulation Methods of Single and Multi-Bit Continuous Time Sigma Delta Modulators

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    Continuous time Sigma Delta Modulators (CT ΣΔMs) are a type of analog to digital converter (ADC) that are used in mixed signal systems to convert analog signals into digital signals. ADCs typically require antialiasing filter; however antialiasing filters are inherent in CT ΣΔMs, and therefore they require less circuitry and less power than other ADC architectures that require separate antialiasing filters. As a result, CT ΣΔM ADC architectures are preferred in many mixed signal electronic applications. Because of the mixed signal nature of CT ΣΔMs, they can be difficult to simulate. In this thesis, various methods for simulating single-bit and multi-bit CT ΣΔMs are developed and these simulations include the bilinear transform or trapezoidal integration, impulse invariance transform, midpoint integration, Simpson’s rule, delta transform or Euler’s forward integration rule and Simulink modeling. These methods are compared with respect to speed which is given by the total simulation time, accuracy which is given by the signal to noise ratio (SNR) value and the simplicity of the simulation method. The CT ΣΔMs have been extended from first order up to fifth order with one, two and three bit quantizers. Also, the frequency domain analysis is done for all the orders of CT ΣΔMs. The results show that the numerical integration methods are more accurate and faster than Simulink. However, CT ΣΔM simulations using Simulink are simpler because of the availability of the required blocks in Simulink. The overall comparison shows that the numerical integration methods can perform better than Simulink models. The frequency domain analysis proves the correctness of the use of numerical integration methods for CT ΣΔM simulations

    Noise Weighting in the Design of {\Delta}{\Sigma} Modulators (with a Psychoacoustic Coder as an Example)

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    A design flow for {\Delta}{\Sigma} modulators is illustrated, allowing quantization noise to be shaped according to an arbitrary weighting profile. Being based on FIR NTFs, possibly with high order, the flow is best suited for digital architectures. The work builds on a recent proposal where the modulator is matched to the reconstruction filter, showing that this type of optimization can benefit a wide range of applications where noise (including in-band noise) is known to have a different impact at different frequencies. The design of a multiband modulator, a modulator avoiding DC noise, and an audio modulator capable of distributing quantization artifacts according to a psychoacoustic model are discussed as examples. A software toolbox is provided as a general design aid and to replicate the proposed results.Comment: 5 pages, 18 figures, journal. Code accompanying the paper is available at http://pydsm.googlecode.co
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