Satisfiability Modulo Theory based Methodology for Floorplanning in VLSI Circuits

This paper proposes a Satisfiability Modulo Theory based formulation for floorplanning in VLSI circuits. The proposed approach allows a number of fixed blocks to be placed within a layout region without overlapping and at the same time minimizing the area of the layout region. The proposed approach is extended to allow a number of fixed blocks with ability to rotate and flexible blocks (with variable width and height) to be placed within a layout without overlap. Our target in all cases is reduction in area occupied on a chip which is of vital importance in obtaining a good circuit design. Satisfiability Modulo Theory combines the problem of Boolean satisfiability with domains such as convex optimization. Satisfiability Modulo Theory provides a richer modeling language than is possible with pure Boolean SAT formulas. We have conducted our experiments on MCNC and GSRC benchmark circuits to calculate the total area occupied, amount of deadspace and the total CPU time consumed while placing the blocks without overlapping. The results obtained shows clearly that the amount of dead space or wasted space is reduced if rotation is applied to the blocks.Comment: 8 pages,5 figure

Per-RMAP: Feasibility-Seeking and Superiorization Methods for Floorplanning with I/O Assignment

The feasibility-seeking approach provides a systematic scheme to manage and solve complex constraints for continuous problems, and we explore it for the floorplanning problems with increasingly heterogeneous constraints. The classic legality constraints can be formulated as the union of convex sets. However, the convergence of conventional projection-based algorithms is not guaranteed as the constrain sets are non-convex. In this work, we propose a resetting strategy to greatly eliminate the the divergence issue of the projection-based algorithm for the feasibility-seeking formulation. Furthermore, the superiorization methodology (SM), which lies between feasibility-seeking and constrained optimization, is firstly applied to floorplanning. The SM uses perturbations to steer the feasibility-seeking algorithm to a feasible solution with shorter total wirelength. The proposed flow is extendable to tackle various constraints and variants of floorplanning problems, e.g., floorplanning with I/O assignment problems. We have evaluated the proposed algorithm on the MCNC benchmarks. We can obtain legal floorplans only two times slower than the branch-and-bound method in its current prototype using MATLAB, with only 3% wirelength inferior to the optimal results. We evaluate the effectiveness of the flow by considering the constraints of I/O assignment, and our algorithm achieve 8% improvement on wirelength.Comment: Accepted for presentation at the International Symposium of EDA (Electronics Design Automation) ISEDA-2023, Nanjing, China, May 8-11, 202

Voltage island-driven floorplanning.

Ma, Qiang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2008.Includes bibliographical references (leaves 78-80).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- Floorplanning --- p.2Chapter 1.3 --- Motivations --- p.4Chapter 1.4 --- Design Implementation of Voltage Islands --- p.5Chapter 1.5 --- Problem Formulation --- p.8Chapter 1.6 --- Progress on the Problem --- p.10Chapter 1.7 --- Contributions --- p.12Chapter 1.8 --- Thesis Organization --- p.14Chapter 2 --- Literature Review on MSV --- p.15Chapter 2.1 --- Introduction --- p.15Chapter 2.2 --- MSV at Post-floorplan/Post Placement Stage --- p.16Chapter 2.2.1 --- """Post-Placement Voltage Island Generation under Performance Requirement""" --- p.16Chapter 2.2.2 --- """Post-Placement Voltage Island Generation""" --- p.18Chapter 2.2.3 --- """Timing-Constrained and Voltage-Island-Aware Voltage Assignment""" --- p.19Chapter 2.2.4 --- """Voltage Island Generation under Performance Requirement for SoC Designs""" --- p.20Chapter 2.2.5 --- """An ILP Algorithm for Post-Floorplanning Voltage-Island Generation Considering Power-Network Planning""" --- p.21Chapter 2.3 --- MSV at Floorplan/Placement Stage --- p.22Chapter 2.3.1 --- """Architecting Voltage Islands in Core-based System-on-a- Chip Designs""" --- p.22Chapter 2.3.2 --- """Voltage Island Aware Floorplanning for Power and Timing Optimization""" --- p.23Chapter 2.4 --- Summary --- p.27Chapter 3 --- MSV Driven Floorplanning --- p.29Chapter 3.1 --- Introduction --- p.29Chapter 3.2 --- Problem Formulation --- p.32Chapter 3.3 --- Algorithm Overview --- p.33Chapter 3.4 --- Optimal Island Partitioning and Voltage Assignment --- p.33Chapter 3.4.1 --- Voltage Islands in Non-subtrees --- p.35Chapter 3.4.2 --- Proof of Optimality --- p.36Chapter 3.4.3 --- Handling Island with Power Down Mode --- p.37Chapter 3.4.4 --- Speedup in Implementation and Complexity --- p.38Chapter 3.4.5 --- Varying Background Chip-level Voltage --- p.39Chapter 3.5 --- Simulated Annealing --- p.39Chapter 3.5.1 --- Moves --- p.39Chapter 3.5.2 --- Cost Function --- p.40Chapter 3.6 --- Experimental Results --- p.40Chapter 3.6.1 --- Extension to Minimize Level Shifters --- p.45Chapter 3.6.2 --- Extension to Consider Power Network Routing --- p.46Chapter 3.7 --- Summary --- p.46Chapter 4 --- MSV Driven Floorplanning with Timing --- p.49Chapter 4.1 --- Introduction --- p.49Chapter 4.2 --- Problem Formulation --- p.52Chapter 4.3 --- Algorithm Overview --- p.56Chapter 4.4 --- Voltage Assignment Problem --- p.56Chapter 4.4.1 --- Lagrangian Relaxation --- p.58Chapter 4.4.2 --- Transformation into the Primal Minimum Cost Flow Problem --- p.60Chapter 4.4.3 --- Cost-Scaling Algorithm --- p.64Chapter 4.4.4 --- Solution Transformation --- p.66Chapter 4.5 --- Simulated Annealing --- p.69Chapter 4.5.1 --- Moves --- p.69Chapter 4.5.2 --- Speeding up heuristic --- p.69Chapter 4.5.3 --- Cost Function --- p.70Chapter 4.5.4 --- Annealing Schedule --- p.71Chapter 4.6 --- Experimental Results --- p.71Chapter 4.7 --- Summary --- p.72Chapter 5 --- Conclusion --- p.76Bibliography --- p.8

A design flow for performance planning : new paradigms for iteration free synthesis

In conventional design, higher levels of synthesis produce a netlist, from which layout synthesis builds a mask specification for manufacturing. Timing anal ysis is built into a feedback loop to detect timing violations which are then used to update specifications to synthesis. Such iteration is undesirable, and for very high performance designs, infeasible. The problem is likely to become much worse with future generations of technology. To achieve a non-iterative design flow, early synthesis stages should use wire planning to distribute delays over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays

Bus-driven floorplanning.

Law Hoi Ying.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 101-106).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- VLSI Design Cycle --- p.2Chapter 1.2 --- Physical Design Cycle --- p.6Chapter 1.3 --- Floorplanning --- p.10Chapter 1.3.1 --- Floorplanning Objectives --- p.11Chapter 1.3.2 --- Common Approaches --- p.12Chapter 1.3.3 --- Interconnect-Driven Floorplanning --- p.14Chapter 1.4 --- Motivations and Contributions --- p.15Chapter 1.5 --- Organization of the Thesis --- p.17Chapter 2 --- Literature Review on 2D Floorplan Representations --- p.18Chapter 2.1 --- Types of Floorplans --- p.18Chapter 2.2 --- Floorplan Representations --- p.20Chapter 2.2.1 --- Slicing Floorplan --- p.21Chapter 2.2.2 --- Non-slicing Floorplan --- p.22Chapter 2.2.3 --- Mosaic Floorplan --- p.30Chapter 2.3 --- Summary --- p.35Chapter 3 --- Literature Review on 3D Floorplan Representations --- p.37Chapter 3.1 --- Introduction --- p.37Chapter 3.2 --- Problem Formulation --- p.38Chapter 3.3 --- Previous Work --- p.38Chapter 3.4 --- Summary --- p.42Chapter 4 --- Literature Review on Bus-Driven Floorplanning --- p.44Chapter 4.1 --- Problem Formulation --- p.44Chapter 4.2 --- Previous Work --- p.45Chapter 4.2.1 --- Abutment Constraint --- p.45Chapter 4.2.2 --- Alignment Constraint --- p.49Chapter 4.2.3 --- Bus-Driven Floorplanning --- p.52Chapter 4.3 --- Summary --- p.53Chapter 5 --- Multi-Bend Bus-Driven Floorplanning --- p.55Chapter 5.1 --- Introduction --- p.55Chapter 5.2 --- Problem Formulation --- p.56Chapter 5.3 --- Methodology --- p.57Chapter 5.3.1 --- Shape Validation --- p.58Chapter 5.3.2 --- Bus Ordering --- p.65Chapter 5.3.3 --- Floorplan Realization --- p.72Chapter 5.3.4 --- Simulated Annealing --- p.73Chapter 5.3.5 --- Soft Block Adjustment --- p.75Chapter 5.4 --- Experimental Results --- p.75Chapter 5.5 --- Summary --- p.77Chapter 6 --- Bus-Driven Floorplanning for 3D Chips --- p.80Chapter 6.1 --- Introduction --- p.80Chapter 6.2 --- Problem Formulation --- p.81Chapter 6.3 --- The Representation --- p.82Chapter 6.3.1 --- Overview --- p.82Chapter 6.3.2 --- Review of TCG --- p.83Chapter 6.3.3 --- Layered Transitive Closure Graph (LTCG) --- p.84Chapter 6.3.4 --- Aligning Blocks --- p.85Chapter 6.3.5 --- Solution Perturbation --- p.87Chapter 6.4 --- Simulated Annealing --- p.92Chapter 6.5 --- Soft Block Adjustment --- p.92Chapter 6.6 --- Experimental Results --- p.93Chapter 6.7 --- Summary --- p.94Chapter 6.8 --- Acknowledgement --- p.95Chapter 7 --- Conclusion --- p.99Bibliography --- p.10

Simultaneous block and I/O buffer floorplanning for flip-chip design

The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip-chip designs is that the input/output buffers could be placed anywhere inside a chip. In this paper, we first introduce the floorplanning problem for the flip-chip design and formulate it as assigning the positions of input/output buffers and first-stage/last-stage blocks so that the path length between blocks and bump balls as well as the delay skew of the paths are simultaneously minimized. We then present a hierarchical method to solve the problem. We first cluster a block and its corresponding buffers to reduce the problem size. Then, we go into iterations of the alternating and interacting global optimization step and the partitioning step. The global optimization step places blocks based on simulated annealing using the B*-tree representation to minimize a given cost function. The partitioning step dissects the chip into two subregions, and the blocks are divided into two groups and are placed in respective subregions. The two steps repeat until each subregion contains at most a given number of blocks, defined by the ratio of the total block area to the chip area. At last, we refine the floorplan by perturbing blocks inside a subregion as well as in different subregions. Compared with the B*-tree based floorplanner alone, our method is more efficient and obtains significantly better results, with an average cost of only 51.8 % of that obtained by using the B*-tree alone, based on a set of real industrial flip-chip designs provided by leading companies

Scalability and interconnection issues in floorplan design and floorplan representations.

Yuen Wing-seung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.Includes bibliographical references (leaves [116]-[122]).Abstracts in English and Chinese.Abstract --- p.iAcknowledgments --- p.iiiList of Figures --- p.viiiList of Tables --- p.xiiChapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivations and Aims --- p.1Chapter 1.2 --- Contributions --- p.3Chapter 1.3 --- Dissertation Overview --- p.4Chapter 2 --- Physical Design and Floorplanning in VLSI Circuits --- p.6Chapter 2.1 --- VLSI Design Flow --- p.6Chapter 2.2 --- Floorplan Design --- p.8Chapter 2.2.1 --- Problem Formulation --- p.9Chapter 2.2.2 --- Types of Floorplan --- p.10Chapter 3 --- Floorplanning Representations --- p.12Chapter 3.1 --- Polish Expression(PE) [WL86] --- p.12Chapter 3.2 --- Bounded-Sliceline-Grid(BSG) [NFMK96] --- p.14Chapter 3.3 --- Sequence Pair(SP) [MFNK95] --- p.17Chapter 3.4 --- O-tree(OT) [GCY99] --- p.19Chapter 3.5 --- B*-tree(BT) [CCWW00] --- p.21Chapter 3.6 --- Corner Block List(CBL) [HHC+00] --- p.22Chapter 4 --- Optimization Technique in Floorplan Design --- p.27Chapter 4.1 --- General Optimization Methods --- p.27Chapter 4.1.1 --- Simulated Annealing --- p.27Chapter 4.1.2 --- Genetic Algorithm --- p.29Chapter 4.1.3 --- Integer Programming Method --- p.31Chapter 4.2 --- Shape Optimization --- p.33Chapter 4.2.1 --- Shape Curve --- p.33Chapter 4.2.2 --- Lagrangian Relaxation --- p.34Chapter 5 --- Literature Review on Interconnect Driven Floorplanning --- p.37Chapter 5.1 --- Placement Constraint in Floorplan Design --- p.37Chapter 5.1.1 --- Boundary Constraints --- p.37Chapter 5.1.2 --- Pre-placed Constraints --- p.39Chapter 5.1.3 --- Range Constraints --- p.41Chapter 5.1.4 --- Symmetry Constraints --- p.42Chapter 5.2 --- Timing Analysis Method --- p.43Chapter 5.3 --- Buffer Block Planning and Congestion Control --- p.45Chapter 5.3.1 --- Buffer Block Planning --- p.45Chapter 5.3.2 --- Congestion Control --- p.50Chapter 6 --- Clustering Constraint in Floorplan Design --- p.53Chapter 6.1 --- Problem Definition --- p.53Chapter 6.2 --- Overview --- p.54Chapter 6.3 --- Locating Neighboring Modules --- p.56Chapter 6.4 --- Constraint Satisfaction --- p.62Chapter 6.5 --- Multi-clustering Extension --- p.64Chapter 6.6 --- Cost Function --- p.64Chapter 6.7 --- Experimental Results --- p.65Chapter 7 --- Interconnect Driven Multilevel Floorplanning Approach --- p.69Chapter 7.1 --- Multilevel Partitioning --- p.69Chapter 7.1.1 --- Coarsening Phase --- p.70Chapter 7.1.2 --- Refinement Phase --- p.70Chapter 7.2 --- Overview of Multilevel Floorplanner --- p.72Chapter 7.3 --- Clustering Phase --- p.73Chapter 7.3.1 --- Clustering Methods --- p.73Chapter 7.3.2 --- Area Ratio Constraints --- p.75Chapter 7.3.3 --- Clustering Velocity --- p.76Chapter 7.4 --- Refinement Phase --- p.77Chapter 7.4.1 --- Temperature Control --- p.79Chapter 7.4.2 --- Cost Function --- p.80Chapter 7.4.3 --- Handling Shape Flexibility --- p.80Chapter 7.5 --- Experimental Results --- p.81Chapter 7.5.1 --- Data Set Generation --- p.82Chapter 7.5.2 --- Temperature Control --- p.82Chapter 7.5.3 --- Packing Results --- p.83Chapter 8 --- Study of Non-slicing Floorplan Representations --- p.89Chapter 8.1 --- Analysis of Different Floorplan Representations --- p.89Chapter 8.1.1 --- Complexity --- p.90Chapter 8.1.2 --- Types of Floorplans --- p.92Chapter 8.2 --- T-junction Orientation Property --- p.97Chapter 8.3 --- Twin Binary Tree Representation for Mosaic Floorplan --- p.103Chapter 8.3.1 --- Previous work --- p.103Chapter 8.3.2 --- Twin Binary Tree Construction --- p.105Chapter 8.3.3 --- Floorplan Construction --- p.109Chapter 9 --- Conclusion --- p.114Chapter 9.1 --- Summary --- p.114Bibliography --- p.116Chapter A --- Clustering Constraint Data Set --- p.123Chapter A.1 --- ami33 --- p.123Chapter A.1.1 --- One cluster --- p.123Chapter A.1.2 --- Multi-cluster --- p.123Chapter A.2 --- ami49 --- p.124Chapter A.2.1 --- One cluster --- p.124Chapter A.2.2 --- Multi-cluster --- p.124Chapter A.3 --- playout --- p.124Chapter A.3.1 --- One cluster --- p.124Chapter A.3.2 --- Multi-cluster --- p.125Chapter B --- Multilevel Data Set --- p.126Chapter B.l --- data_100 --- p.126Chapter B.2 --- data_200 --- p.127Chapter B.3 --- data_300 --- p.129Chapter B.4 --- data_400 --- p.131Chapter B.5 --- data_500 --- p.13