An Efficient Medium Access Control Strategy for High Speed WDM Multiaccess Networks

A medium access control (MAC) strategy that accounts for the limited tunability of present-day lasers and filters and yet supports a large total number of wavelengths in the network is proposed. Full interconnectivity, contention-free access and a high value of concurrency are achieved by dividing the network into disjunct subnetworks on a wavelength basis and by reconfiguring these subnetworks on a time basis. Each subnetwork allows for simplified access to be implemented with fast tunable transceivers each assessing only a moderate number of wavelengths. A performance analysis shows that this concept is most efficient when applied to a high-level broadband interconnection metropolitan area network (MAN

Symmetric rearrangeable networks and algorithms

A class of symmetric rearrangeable nonblocking networks has been considered in this thesis. A particular focus of this thesis is on Benes networks built with 2 x 2 switching elements. Symmetric rearrangeable networks built with larger switching elements have also being considered. New applications of these networks are found in the areas of System on Chip (SoC) and Network on Chip (NoC). Deterministic routing algorithms used in NoC applications suffer low scalability and slow execution time. On the other hand, faster algorithms are blocking and thus limit throughput. This will be an acceptable trade-off for many applications where achieving ”wire speed” on the on-chip network would require extensive optimisation of the attached devices. In this thesis I designed an algorithm that has much lower blocking probabilities than other suboptimal algorithms but a much faster execution time than deterministic routing algorithms. The suboptimal method uses the looping algorithm in its outermost stages and then in the two distinct subnetworks deeper in the switch uses a fast but suboptimal path search method to find available paths. The worst case time complexity of this new routing method is O(NlogN) using a single processor, which matches the best known results reported in the literature. Disruption of the ongoing communications in this class of networks during rearrangements is an open issue. In this thesis I explored a modification of the topology of these networks which gives rise to what is termed as repackable networks. A repackable topology allows rearrangements of paths without intermittently losing connectivity by breaking the existing communication paths momentarily. The repackable network structure proposed in this thesis is efficient in its use of hardware when compared to other proposals in the literature. As most of the deterministic algorithms designed for Benes networks implement a permutation of all inputs to find the routing tags for the requested inputoutput pairs, I proposed a new algorithm that can work for partial permutations. If the network load is defined as ρ, the mean number of active inputs in a partial permutation is, m = ρN, where N is the network size. This new method is based on mapping the network stages into a set of sub-matrices and then determines the routing tags for each pair of requests by populating the cells of the sub-matrices without creating a blocking state. Overall the serial time complexity of this method is O(NlogN) and O(mlogN) where all N inputs are active and with m < N active inputs respectively. With minor modification to the serial algorithm this method can be made to work in the parallel domain. The time complexity of this routing algorithm in a parallel machine with N completely connected processors is O(log^2 N). With m active requests the time complexity goes down to (logmlogN), which is better than the O(log^2 m + logN), reported in the literature for 2^0.5((log^2 -4logN)^0.5-logN)<= ρ <= 1. I also designed multistage symmetric rearrangeable networks using larger switching elements and implement a new routing algorithm for these classes of networks. The network topology and routing algorithms presented in this thesis should allow large scale networks of modest cost, with low setup times and moderate blocking rates, to be constructed. Such switching networks will be required to meet the bandwidth requirements of future communication networks

Design of Routers for Optical Burst Switched Networks

Optical Burst Switching (OBS) is an experimental network technology that enables the construction of very high capacity routers using optical data paths and electronic control. In this dissertation, we study the design of network components that are needed to build an OBS network. Specifically, we study the design of the switches that form the optical data path through the network. An OBS network that switches data across wavelength channels requires wave-length converting switches to construct an OBS router. We study one particular design of wavelength converting switches that uses tunable lasers and wavelength grating routers. This design is interesting because wavelength grating routers are passive devices and are much less complex and hence less expensive than optical crossbars. We show how the routing problem for these switches can be formulated as a combinatorial puzzle or game, in which the design of the game board determines key performance characteristics of the switch. In this disertation, we use this formu-lation to facilitate the design of switches and associated routing strategies with good performance. We then introduce time sliced optical burst switching (TSOBS), a variant of OBS that switches data in the time domain rather that the wavelength domain. This eliminates the need for wavelength converters, the largest single cost component of systems that switch in the wavelength domain. We study the performance of TSOBS networks and discuss various design issues. One of the main components that is needed to build a TSOBS router is an optical time slot interchanger (OTSI). We explore various design options for OTSIs. Finally, we discuss the issues involved in the design of network interfaces that transmit the data from hosts that use legacy protocols into a TSOBS network. Ag-gregation and load balancing are the main issues that determine the performance of a TSOBS network and we develop and evaluate methods for both

Application of advanced on-board processing concepts to future satellite communications systems

An initial definition of on-board processing requirements for an advanced satellite communications system to service domestic markets in the 1990's is presented. An exemplar system architecture with both RF on-board switching and demodulation/remodulation baseband processing was used to identify important issues related to system implementation, cost, and technology development

Architectures of new switching systems.

by Lam Wan.Thesis submitted in: November 1997.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 96-102).Abstract also in Chinese.Part IChapter 1 --- Introduction to Integrated Intelligent Personal Communication System --- p.1Chapter 2 --- The Switching Architecture --- p.5Chapter 2.1 --- The Overall Switching Architecture --- p.6Chapter 2.2 --- Switching Module --- p.10Chapter 2.2.1 --- Traffic Routing in Switching Module --- p.11Chapter 2.2.2 --- Structure of Switching Module --- p.15Chapter 2.2.3 --- Wireless Base Interface --- p.16Chapter 2.2.4 --- Trunk Interface --- p.18Chapter 2.2.5 --- Analog Interfaces --- p.18Chapter 2.3 --- Network Intelligence --- p.19Chapter 2.4 --- Wireless Part --- p.21Chapter 2.4.1 --- Call-Setup in IIPCS --- p.24Chapter 2.4.2 --- Handoff --- p.25Chapter 2.4.3 --- Wireless Base --- p.27Chapter 2.5 --- Downstream Wired Extensions --- p.28Chapter 2.6 --- Upstream Wired Part --- p.28Chapter 2.7 --- Voice System --- p.28Chapter 2.8 --- Features of the IIPCS --- p.29Chapter 3 --- Concluding Remarks --- p.33Chapter 3.1 --- Summary --- p.35Chapter 3.2 --- Directions for Further Research --- p.36Part IIChapter 4 --- Introduction to Next-Generation Switch --- p.37Chapter 5 --- Architecture of Next-Generation Switch --- p.41Chapter 5.1 --- Overall Architecture of Next-Generation Switch --- p.42Chapter 5.1.1 --- Interface module --- p.44Chapter 5.1.2 --- Packetizer --- p.46Chapter 5.2 --- Concentration Fabric --- p.50Chapter 5.3 --- Shared-Buffer Memory Switch --- p.53Chapter 6 --- Concentration Networks --- p.56Chapter 6.1 --- Background of Concentration Networks --- p.56Chapter 6.2 --- k-Sorting --- p.63Chapter 6.3 --- Concentrator --- p.72Chapter 6.3.1 --- Nk-to-k Concentrator --- p.73Chapter 6.3.2 --- Match between Circles with Cost Reduction --- p.75Chapter 6.4 --- The Structure of a Molecule --- p.78Chapter 6.5 --- Summary --- p.81Chapter 7 --- Lock-Latch Algorithm --- p.82Chapter 8 --- Performance Evaluation --- p.88Chapter 9 --- Concluding Remarks --- p.93Chapter 9.1 --- LSI Implementation --- p.94Chapter 9.2 --- Summary --- p.95Bibliograph

Random Routing and Concentration in Quantum Switching Networks

Flexible distribution of data in the form of quantum bits or qubits among spatially separated entities is an essential component of envisioned scalable quantum computing architectures. Accordingly, we consider the problem of dynamically permuting groups of quantum bits, i.e., qubit packets, using networks of reconfigurable quantum switches. We demonstrate and then explore the equivalence between the quantum process of creation of packet superpositions and the process of randomly routing packets in the corresponding classical network. In particular, we consider an n &times; n Baseline network for which we explicitly relate the pairwise input-output routing probabilities in the classical random routing scenario to the probability amplitudes of the individual packet patterns superposed in the quantum output state. We then analyze the effect of using quantum random routing on a classically non-blocking configuration like the Benes network. We prove that for an n &times; n quantum Benes network, any input packet assignment with no output contention is probabilistically self-routable. In particular, we prove that with random routing on the first (log n-1) stages and bit controlled self-routing on the last log n stages of a quantum Benes network, the output packet pattern corresponding to routing with no blocking is always present in the output quantum state with a non-zero probability. We give a lower bound on the probability of observing such patterns on measurement at the output and identify a class of 2n-1 permutation patterns for which this bound is equal to 1, i.e., for all the permutation patterns in this class the following is true: in every pattern in the quantum output assignment all the valid input packets are present at their correct output addresses. In the second part of this thesis we give the complete design of quantum sparse crossbar concentrators. Sparse crossbar concentrators are rectangular grids of simple 2 &times; 2 switches or crosspoints, with the switches arranged such that any k inputs can be connected to some k outputs. We give the design of the quantum crosspoints for such concentrators and devise a self-routing method to concentrate quantum packets. Our main result is a rigorous proof that certain crossbar structures, namely, the fat-slim and banded quantum crossbars allow, without blocking, the realization of all concentration patterns with self-routing. In the last part we consider the scenario in which quantum packets are queued at the inputs to an n &times; n quantum non-blocking switch. We assume that each packet is a superposition of m classical packets. Under the assumption of uniform traffic, i.e., any output is equally likely to be accessed by a packet at an input we find the minimum value of m such that the output quantum state contains at least one packet pattern in which no two packets contend for the same output. Our calculations show that for m=9 the probability of a non-contending output pattern occurring in the quantum output is greater than 0.99 for all n up to 64

An Expandable Architecture for a Conferencing Digital Communications Switch

This paper architecturally describes the switching portion of a digital communications system that is dedicated to conferencing. The basic ideas and methods of circuit switching and packet switching are introduced. The conferencing function is described, and some resulting design considerations are discussed. The architecture of the switch is then presented. Circuit switching techniques are used throughout the architecture of the switch, coupled with arithmetic processing to accomplish the conferencing function. The architecture is developed in such a way that it is expandable in all directions to meet a given set of requirements. The requirements include the number of users the system supports and the number of conference channels provided. The processing stages of the switch can be sized based on these requirements and the chosen component speeds. The basic timing of each stage is given to describe its operation and establish the critical delay paths. The resulting switching methods first introduced. The switch is also tested to see if it fits the criteria for being a distributed processing system. It is concluded that if the provision for dynamic reconfiguration is added, the switch fits the criteria. Finally, further topics of study are suggested

Models for planning the evolution of local telecommunication networks

Includes bibliographical references.Research initiated through a grant from GTE Laboratories, Inc. Supported in part by an AT&T research award. Supported in part by the Systems Theory and Operations Research Program of the National Science Foundation. ECS-8316224 Supported in part by ONR. N0000-14-86-0689A. Balakrishnan ... [et al.]