Dielectric Breakdown in Chemical Vapor Deposited Hexagonal Boron Nitride

Insulating films are essential in multiple electronic devices because they can provide essential functionalities, such as capacitance effects and electrical fields. Two-dimensional (2D) layered materials have superb electronic, physical, chemical, thermal, and optical properties, and they can be effectively used to provide additional performances, such as flexibility and transparency. 2D layered insulators are called to be essential in future electronic devices, but their reliability, degradation kinetics, and dielectric breakdown (BD) process are still not understood. In this work, the dielectric breakdown process of multilayer hexagonal boron nitride (h-BN) is analyzed on the nanoscale and on the device level, and the experimental results are studied via theoretical models. It is found that under electrical stress, local charge accumulation and charge trapping/detrapping are the onset mechanisms for dielectric BD formation. By means of conductive atomic force microscopy, the BD event was triggered at several locations on the surface of different dielectrics (SiO2, HfO2, Al2O3, multilayer h-BN, and monolayer h-BN); BD-induced hillocks rapidly appeared on the surface of all of them when the BD was reached, except in monolayer h-BN. The high thermal conductivity of h-BN combined with the one-atom-thick nature are genuine factors contributing to heat dissipation at the BD spot, which avoids self-accelerated and thermally driven catastrophic BD. These results point to monolayer h-BN as a sublime dielectric in terms of reliability, which may have important implications in future digital electronic devices.Fil: Jiang, Lanlan. Soochow University; ChinaFil: Shi, Yuanyuan. Soochow University; China. University of Stanford; Estados UnidosFil: Hui, Fei. Soochow University; China. Massachusetts Institute of Technology; Estados UnidosFil: Tang, Kechao. University of Stanford; Estados UnidosFil: Wu, Qian. Soochow University; ChinaFil: Pan, Chengbin. Soochow University; ChinaFil: Jing, Xu. Soochow University; China. University of Texas at Austin; Estados UnidosFil: Uppal, Hasan. University of Manchester; Reino UnidoFil: Palumbo, Félix Roberto Mario. Comisión Nacional de Energía Atómica; Argentina. Universidad Tecnológica Nacional; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Lu, Guangyuan. Chinese Academy of Sciences; República de ChinaFil: Wu, Tianru. Chinese Academy of Sciences; República de ChinaFil: Wang, Haomin. Chinese Academy of Sciences; República de ChinaFil: Villena, Marco A.. Soochow University; ChinaFil: Xie, Xiaoming. Chinese Academy of Sciences; República de China. ShanghaiTech University; ChinaFil: McIntyre, Paul C.. University of Stanford; Estados UnidosFil: Lanza, Mario. Soochow University; Chin

Electrical properties of ultra thin Al2O3 and HfO2 films as gate dielectrics in MOS technology

The rapidly evolving silicon industry demands devices with high-speed and low power consumption. This has led to aggressive scaling of the dimensions in metal oxide semiconductor field effect transistors (MOSFETs). The channel length has been reduced as a result of this scaling. The industry favorite, SlO2, has reached limitations in the thickness regime of 1-1.5 nm as a gate dielectric. High-κ gate dielectrics such as Al203 and HfO2 and their silicates are some of the materials that may, probably, replace SlO2, as gate dielectric in the next four to five years. The present study is an attempt to understand the electrical characteristics of these exciting materials grown by atomic layer deposition (ALD) technique. The flat band voltages (VFB) were determined from C-V measurements on circularly patterned MOS capacitors. For phosphorous doped polysilicon electrodes and Al-oxide based dielectrics, positive shifts in VFB were observed, relative to a pure SlO2 control, ranging from 0.2 to 0.8V. It is believed that this is caused by fixed charges. Rapid thermal annealing at 1000°C tends to decrease VFB relative to a 800°C anneal. Changes in VFB UP to 0.35 V are observed for films deposited over SlO2 underlayers, while smaller changes, up to 0.05 V, are observed for films deposited directly on Si. Spike annealing is also observed to reduce oxide leakage. HfO2 showed large amount of leakage resulting in difficulty in performing capacitance measurements. ZrO2 was found to be reacting with polycrystalline silicon and thus high leakage current was observed

A Review on Conduction Mechanisms in Dielectric Films

The conduction mechanisms in dielectric films are crucial to the successful applications of dielectric materials. There are two types of conduction mechanisms in dielectric films, that is, electrode-limited conduction mechanism and bulk-limited conduction mechanism. The electrode-limited conduction mechanism depends on the electrical properties at the electrode-dielectric interface. Based on this type of conduction mechanism, the physical properties of the barrier height at the electrode-dielectric interface and the effective mass of the conduction carriers in dielectric films can be extracted. The bulk-limited conduction mechanism depends on the electrical properties of the dielectric itself. According to the analyses of bulk-limited conduction mechanisms, several important physical parameters in the dielectric films can be obtained, including the trap level, the trap spacing, the trap density, the carrier drift mobility, the dielectric relaxation time, and the density of states in the conduction band. In this paper, the analytical methods of conduction mechanisms in dielectric films are discussed in detail

Heteroepitaxy of semiconductor-insulator layers and their interface properties

The epitaxial growth of Ba₂SiO₄ thin films on Si(001) by co-deposition of Ba and Si in an oxygen background pressure is systematically investigated with a focus on the epitaxial interface. A structural investigation is performed by employing x-ray photoelectron spectroscopy (XPS), low energy electron diffraction (LEED) and aberration-corrected scanning transmission electron microscopy (STEM). In addition, an electrical characterization is done using MOS test capacitors. The stoichiometry at the interface turns out to be critically dependent on the oxygen background pressure during deposition. Films grown with an oxygen pressure just above the saturation point for a complete oxidation of the film still feature 1/4 ML of O atoms in Si-O-Si bonding states. In comparison, the Ba₂SiO₄ bulk structure has only O atoms in Si-O-Ba bonding states. STEM shows that these films form an atomically sharp interface to Si(001) and that the Ba₂SiO₄ bulk structure is maintained up to the penultimate layer at the interface. Only one silicate layer is changed to a (2x3) structure, which is also observed in LEED, to match the (2x1.5) bulk structure to Si(001), neglecting relaxations. An interface model is proposed for these films, which features a pseudo-(2x1) reconstruction of the Si surface and helps to understand the formation process of the epitaxial interface in greater detail. The growth in a high oxygen pressure leads to the formation of Si-rich silicate at the interface, which does not prevent the epitaxial growth but modifies the interface into a (2x6) structure. Moreover, a Ba surplus results in the formation of interfacial silicide, which is characterized by a (4x2) structure. A dielectric constant of k=22.5 ± 1.1 is found for Ba₂SiO₄, as well as band offsets to Si(001) larger than 1.8 eV for crystalline layers. Moreover, leakage current densities as low as 2 ⋅ 10⁻⁶ A/cm² at -1 V are measured for a 10 nm thick film. Interface trap densities at midgap of (1.14 ± 0.78) ⋅ 10¹² eV⁻¹cm⁻¹² are measured for crystalline films with an abrupt interface. Amorphous films show slightly higher interface trap densities of (2.72 ± 0.82) ⋅ 10¹² eV⁻¹cm⁻¹² at midgap. A further reduction of the interface trap density is possible by incorporating a Si-rich silicate layer at the interface, which results in interface trap densities of (3.32 ± 0.45) ⋅ 10¹¹ eV⁻¹cm⁻¹² at midgap for crystalline layers. However, even though no SiO₂ forms at the interface, the epitaxial interface still contributes an offset of (0.56 ± 0.08) nm to the overall CET, which greatly limits the achievable minimum CET of the gate stack

PHONON-ENERGY-COUPLING-ENHANCEMENT EFFECT AND ITS APPLICATIONS

Silicon Oxide/Oxynitride (SiO2/SiON) has been the mainstream material used for gate dielectric for MOS transistors for the past 30 years. The aggressive scaling of the feature size of MOS transistor has limited the ability of SiO2/SiON to work effectively as the gate dielectric to modulate the conduction of current of MOS transistors due to excess leakage current dominated by direct quantum tunneling. Due to this constraint, alternative gate dielectric/high-k is being employed to reduce the leakage current in order to maintain the rate of scaling of MOS transistors. However, the cost involved in the implementation of these new gate dielectric materials are high due to the requirements of a change in the process flow for device fabrication. This work presents the results of a novel processing method implementing the use of rapid thermal processing (RTP) on conventional SiO2/SiON gate dielectric to reduce the gate leakage current by three to five orders of magnitude. Electrical properties of the effect were characterized on fabricated MOS capacitors using semiconductor parameter analyzer and LCR meter. Material characterization was performed using FT-IR to understand the mechanism involved in this novel processing method, named PECE (Phonon-Energy-Coupling-Enhancement). By implementing this novel process, the use of SiO2/SiON as gate dielectric can be scaled further in conventional process flow of device fabrication

Doped And Chemically Transformed Transition Metal Dichalcogenides (tmdcs) For Two-Dimensional (2d) Electronics

Transition metal dichalcogenides (TMDCs) as the semiconductor counterparts of gra-phene have emerged as promising channel materials for flexible electronic and optoelectronic devices. The 2D layer structure of TMDCs enables the ultimate scaling of TMDC-based devices down to atomic thickness. Furthermore, the absence of dangling bonds in these materials helps to form high quality heterostructures with ultra-clean interfaces. The main objective of this work is to develop novel approaches to fabricating TMDC-based 2D electronic devices such as diodes and transistors. In the first part, we have fabricated 2D p-n junction diodes through van der Waals assembly of heavily p-doped MoS2 (WSe2) and lightly n-doped MoS2 to form vertical homo-(hetero-) junctions, which allows to continuously tune the electron concentration on the n-side for a wide range. In sharp contrast to conventional p-n junction diodes, we have observed nearly exponential dependence of the reverse-current on gate-voltage in our 2D p-n junction devices, which can be attributed to band-to-band tunneling through a gate-tunable tunneling barrier. In the second part, we developed a new strategy to engineer high-κ dielectrics by con-verting atomically thin metallic 2D TMDCs into high-κ dielectrics because it remains a signifi-cant challenge to deposit uniform high-κ dielectric thin films on TMDCs with ALD due to the lack of dangling bonds on the surfaces of TMDCs. In our study, we converted mechanically ex-foliated atomically thin layers of a 2D metal, TaS2 (HfSe2) into a high-κ dielectric, Ta2O5 (HfO2) by thermal oxidation. X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), energy dispersive spectroscopy (EDS), and atomic force microscopy (AFM) were used to understand the phase conversion process. Capacitance-voltage (C-V) measure-ments were carried out to determine the dielectric constant of thermally oxidized dielec-trics. We fabricated MoS2 field-effect transistors (FETs) with thermally oxidized ultra-thin and ultra-smooth Ta2O5 as top-gate and bottom-gate high-κ dielectric layers. We observed promis-ing device performance, including a nearly ideal subthreshold swing of ~ 61 mV/dec at room temperature, negligible hysteresis, drain-current saturation in the output characteristics, a high on/off ratio ~ 106, and a room temperature field-effect mobility exceeding 60 cm2/Vs. To fur-ther reduce the leak current and improve the device performance, we have also investigated the chemical transformation of HfSe2 to HfO2 high-κ dielectric, which has significantly larger band gap than Ta2O5

Germanium MOS devices integrating high-k dielectric and metal gate

textThis dissertation investigates the fabrication and characteristics of the metaloxide-semiconductor (MOS) devices built on germanium substrates integrating HfO2 high-κ dielectric and TaN metal gate electrode. The metal-gate/high-κ/germanium MOS stack, by taking the advantages of the high carrier mobility from the germanium channel and the sub-nm equivalent-oxide-thickness (EOT) scaling capability from the high-κ dielectric and the metal gate electrode, offers a possible solution for the future advanced complementary MOS (CMOS) applications to further boast the transistors’ driving current for faster operation. Due to the unstable and poor-quality natively grown germanium oxide, surface treatment is very critical in germanium device fabrication in order to remove the native oxide and prevent its growth, as well as suppress the interdiffusion across the interface. Several wet cleaning methods and an in situ cleaning technique by Ar anneal have been investigated. Surface passivation techniques, including NH3-based surface nitridation (SN) by forming a GeOxNy layer and silicon interlayer (SiIL) passivation by growing an ultra-thin (several monolayer) silicon layer between the high-κ dielectric and the substrate, have been studied and proved able to improve device performance significantly. Both p- and n-channel germanium transistors have been successfully fabricated. 1.8X enhancement of peak mobility in p-channel and 2.5X in n-channel over the silicon control devices have been achieved. The interface growth mechanism between the germanium substrate and the dielectric layer has been investigated. Two competing processes occurring at the interface determine the formation of the interfacial layer and affect Ge outdiffusion. Substrate dopants are found playing important roles, which causes the variations in the interfacial layer formation on different types of substrates and so on in the electrical properties. The relatively high diffusivity of dopants and germanium atoms in bulk germanium and the induced structural defects near the surface may severely degrade the device performance. This can well explain the very poor performance of the n-channel devices reported recently by several groups. Performance degradation of the germanium devices after thermal anneal, which is resulting from the interdiffusion and germanium oxide desorption, suggests that thermal stability is a concern in high temperature processes and more stable passivation techniques may be required. Long term reliability study indicates that HfO2 dielectric with SN treatment on germanium is robust against TDDB stress and the long term reliability (TDDB) is not a concern for germanium MOS devices.Electrical and Computer Engineerin

Investigation of different dielectric materials as gate insulator for MOSFETs

The scaling of semiconductor transistors has led to a decrease in thickness of the silicon dioxide layer used as gate dielectric. The thickness of the silicon dioxide layer is reduced to increase the gate capacitance, thus increasing the drain current. If the thickness of the gate dielectric decreases below 2nm, the leakage current due to the tunneling increases drastically. Hence it is necessary to replace the gate dielectric, silicon dioxide, with a physically thicker oxide layer of high-k materials like Hafnium oxide and Titanium oxide. High-k dielectric materials allow the capacitance to increase without a huge leakage current. Hafnium oxide and Titanium oxide films are deposited by reactive magnetron sputtering from Hafnium and Titanium targets respectively. These oxide layers are used to create metal-insulator-metal (MIM) structures using aluminum as the top and bottom electrodes. The films are deposited at various O2/Ar gas flow ratios, substrate temperatures, and process pressures. After attaining an exact recipe for these oxide layers that exhibit the desired parameters, MOS capacitors are fabricated with n-Si and p-Si substrates having aluminum electrodes at the top and bottom of each. Comparing the parameters of Hafnium oxide- and Titanium oxide- based MOS capacitors, MOSFET devices are designed with Hafnium oxide as gate dielectric

Fabrication and Characterization of AlGaN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors for High Power Applications

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) are promising candidates for next generation high-efficiency and high-voltage power applications. The excellent physical properties of GaN-based materials, featuring high critical electric field and large carrier saturation velocity, combined to the high carrier density and large mobility of the two-dimensional electron gas confined at the AlGaN/GaN interface, enable higher power density minimizing power losses and self-heating of the device. However, the advent of the GaN-based MIS-HEMT to the industrial production is still hindered by technological challenges that are being faced in parallel. Among them, one of the biggest challenge is represented by the insertion of a gate dielectric in MIS-HEMTs compared to Schottky-gate HEMTs, which causes operational instability due to the presence of high-density trap states located at the dielectric/III-nitride interface or within the dielectric. The development of a gold-free ohmic contact technology is another important concern since the high-volume and cost-effective production of GaN-based transistors also depends on the cooperative manufacturing of GaN-based devices in Si production facilities, where gold represents an undesidered source of contamination. In fact, even though over the past years there have been multiple attemps to develop gold-free ohmic contacts, there is still no full understanding of the contact formation and current transport mechanism. The first objective of this work was the investigation of a gold-free and low-resistive ohmic contact technology to AlGaN/GaN based on sputtered Ta/Al-based metal stacks annealed at low temperatures. A low contact resistance below 1 Ω mm was obtained using Ta/Al-based metal stacks annealed at temperatures below 600 °C. The ohmic behavior and the contact properties of contact resistance, optimum annealing temperature and thermal stability of Ta/Al-based contacts were studied. The nature of the current transport was also investigated indicating a contact mechanism governed by thermionic field emission tunneling through the AlGaN barrier. Finally, gold-free Ta/Al-based ohmic contacts were integrated in MIS-HEMTs fabricated on a 150 mm GaN-on- Si substrate, demonstrating to be a promising contact technology for AlGaN/GaN devices and revealing to be beneficial for devices operating at high temperatures. The optimization of the MIS-gate structure in terms of trap states at the dielectric/III-nitride interface and inside the dielectric in MIS-HEMTs using atomic layer deposited (ALD) Al2O3 as gate insulator was the second focus of this work. First, the MIS-gate structure was improved by an O2 plasma surface preconditioning applied before the Al2O3 deposition and by an N2 postmetallization anneal applied after gate metallization, which significantly reduced trap states at the Al2O3/GaN interface and within the dielectric. Afterwards, the effectiveness of these treatments was demonstrated in Al2O3-AlGaN/GaN MIS-HEMTs by pulsed current–voltage measurements revealing improved threshold voltage stability. Lastly, it was shown that also the lower annealing temperatures used for the formation of Ta/Al-based ohmic contacts, processed before gate dielectric deposition, are beneficial in terms of trap states at the ALD-Al2O3/GaN interface, representing a new aspect to be considered when using an ohmic first fabrication approach