On the asymmetric clocked buffered switch

A $2 times 2$ clocked buffered switch is a device used in data-processing networks for routing messages from one node to another. The message handling process of this switch can be modelled as a two-server, time slotted, queueing process with state space the number of messages ( {bf x_n , {bf y_n ) present at the servers at the end of a time slot. The ({bf x_n , {bf y_n )-process is a two-dimensional nearest-neighbour random walk. In the present study the bivariate generating function $Phi (p , q)$ of the stationary distribution of this random walk is determined, assuming that this distribution exists. $Phi (p, q)$ is known, whenever $Phi (p,0)$ and $Phi ( 0 , q)$ are known. The essential points of the present study are the construction of these two functions from the knowledge of their poles and zeros and the simple determination of these poles and zeros

Deadline-ordered parallel iterative matching with QoS guarantee.

by Lui Hung Ngai.Thesis (M.Phil.)--Chinese University of Hong Kong, 2000.Includes bibliographical references (leaves 56-[59]).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Thesis Overview --- p.3Chapter 2 --- Background & Related work --- p.4Chapter 2.1 --- Scheduling problem in ATM switch --- p.4Chapter 2.2 --- Traffic Scheduling in output-buffered switch --- p.5Chapter 2.3 --- Traffic Scheduling in Input buffered Switch --- p.16Chapter 3 --- Deadline-ordered Parallel Iterative Matching (DLPIM) --- p.22Chapter 3.1 --- Introduction --- p.22Chapter 3.2 --- Switch model --- p.23Chapter 3.3 --- Deadline-ordered Parallel Iterative Matching (DLPIM) --- p.24Chapter 3.3.1 --- Motivation --- p.24Chapter 3.3.2 --- Algorithm --- p.26Chapter 3.3.3 --- An example of DLPIM --- p.28Chapter 3.4 --- Simulation --- p.30Chapter 4 --- DLPIM with static scheduling algorithm --- p.41Chapter 4.1 --- Introduction --- p.41Chapter 4.2 --- Static scheduling algorithm --- p.42Chapter 4.3 --- DLPIM with static scheduling algorithm --- p.48Chapter 4.4 --- An example of DLPIM with static scheduling algorithm --- p.50Chapter 5 --- Conclusion --- p.54Bibliography --- p.5

The compensation approach for three or more dimensional random walks

In this paper we investigate for which random walks with three or more dimensions the compensation approach can be used to determine the equilibrium distribution. As we will see, the compensation approach is not appropriate for the symmetric shortest queue system with three queues, but for the 2 x 3 buffered switch it is. By using this compensation approach, we show that for the 2 x 3 buffered switch the equilibrium distribution can be expressed as a linear combination of six series of binary trees of product-form (geometric) distributions

Asymmetric clock driver for improved power and noise performances

One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an important solution to reduce the switching noise generated by the global clock, with a very reduced degradation in performances and reliability. The suited sizing of clock generators and the design of asymmetric clock tree cells, show the benefits of the proposed technique, validated through a design example where a 50% of noise reduction is achieved with 10% of loss in operation frequency and no penalty, even saving, in power consumption.Ministerio de Educación y Ciencia TEC2004-01509Junta de Andalucía TIC2006-63

Quarc: a novel network-on-chip architecture

This paper introduces the Quarc NoC, a novel NoC architecture inspired by the Spidergon NoC. The Quarc scheme significantly outperforms the Spidergon NoC through balancing the traffic which is the result of the modifications applied to the topology and the routing elements.The proposed architecture is highly efficient in performing collective communication operations including broadcast and multicast. We present the topology, routing discipline and switch architecture for the Quarc NoC and demonstrate the performance with the results obtained from discrete event simulations

SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects

A 64-bit, 8 × 8 mesh network-on-chip (NoC) is presented that uses both new architectural and circuit design techniques to improve on-chip network energy-efficiency, latency, and throughput. First, we propose token flow control, which enables bypassing of flit buffering in routers, thereby reducing buffer size and their power consumption. We also incorporate reduced-swing signaling in on-chip links and crossbars to minimize datapath interconnect energy. The 64-node NoC is experimentally validated with a 2 × 2 test chip in 90 nm, 1.2 V CMOS that incorporates traffic generators to emulate the traffic of the full network. Compared with a fully synthesized baseline 8 × 8 NoC architecture designed to meet the same peak throughput, the fabricated prototype reduces network latency by 20% under uniform random traffic, when both networks are run at their maximum operating frequencies. When operated at the same frequencies, the SWIFT NoC reduces network power by 38% and 25% at saturation and low loads, respectively

The Compensation Approach for Three or More Dimensional Random Walks

In this paper we investigate for which random walks with three or more dimensions the compensation approach can be used to determine the equilibrium distribution. As we will see, the compensation approach is not appropriate for the symmetric shortest queue system with three queues, but for the 2 x 3 buffered switch it is. By using this compensation approach, we show that for the 2 x 3 buffered switch the equilibrium distribution can be expressed as a linear combination of six series of binary trees of product-form (geometric) distributions

The Primordial Inflation Polarization Explorer (PIPER)

The Primordial Inflation Polarization Explorer (PIPER) is a balloon-borne cosmic microwave background (CMB) polarimeter designed to search for evidence of inflation by measuring the large-angular scale CMB polarization signal. BICEP2 recently reported a detection of B-mode power corresponding to the tensor-to-scalar ratio r = 0.2 on ~2 degree scales. If the BICEP2 signal is caused by inflationary gravitational waves (IGWs), then there should be a corresponding increase in B-mode power on angular scales larger than 18 degrees. PIPER is currently the only suborbital instrument capable of fully testing and extending the BICEP2 results by measuring the B-mode power spectrum on angular scales $\theta$ = ~0.6 deg to 90 deg, covering both the reionization bump and recombination peak, with sensitivity to measure the tensor-to-scalar ratio down to r = 0.007, and four frequency bands to distinguish foregrounds. PIPER will accomplish this by mapping 85% of the sky in four frequency bands (200, 270, 350, 600 GHz) over a series of 8 conventional balloon flights from the northern and southern hemispheres. The instrument has background-limited sensitivity provided by fully cryogenic (1.5 K) optics focusing the sky signal onto four 32x40-pixel arrays of time-domain multiplexed Transition-Edge Sensor (TES) bolometers held at 140 mK. Polarization sensitivity and systematic control are provided by front-end Variable-delay Polarization Modulators (VPMs), which rapidly modulate only the polarized sky signal at 3 Hz and allow PIPER to instantaneously measure the full Stokes vector (I, Q, U, V) for each pointing. We describe the PIPER instrument and progress towards its first flight.Comment: 11 pages, 7 figures. To be published in Proceedings of SPIE Volume 9153. Presented at SPIE Astronomical Telescopes + Instrumentation 2014, conference 915