Very large time constant Gm-C Filters

In this study a set of tools for the design of fully integrated transconductor-capacitor (Gm-C) filters, with very large time constants and current consumption under one micro-Ampere are presented. The selected application is a 2nd order bandpass-filter-amplifier, with a gain of 400 from 0.5 to 7Hz, carrying out the signal conditioning of a piezoelectric accelerometer which is part of an implantable cardiac pacemaker. The main challenge is to achieve very large time constants, without using any discrete external component. The chosen circuit technique to fulfill the requirement is series-parallel current division applied to standard symmetrical transconductors (OTAs). These circuits have demonstrated to be an excellent solution regarding their occupied area, power consumption, noise, linearity, and particularly offset. OTAs as low as 33pS -equivalent to a 30G resistor-, with up to 1V linear range, and input referred offset of a few mV, were designed, fabricated in a standard 0.8 micron CMOS technology, and tested. The application requires the series-parallel association of a large number of transistors, and the use of bias currents as low as a few pico-Amperes, which is not very common in analog integrated circuits. In this case the designer should employ maximum care in the selection of the transistor models to be used. A central aspect of this thesis was also to evaluate and develop noise and offset estimation models which was not obvious in the very beginning of the research. In the first two chapters an introduction to the target application is presented, and several MOS transistor characteristics in terms of the inversion coefficient -using the ACM transistor model- are evaluated. In chapter 3 it is discussed whether the usual flicker and thermal noise models are consistent regarding series-parallel association, and adequately represent the expected noise behavior under different bias conditions. A consistent, physics-based, one-equation-all-regions model for flicker noise in the MOS transistor is then presented. Several noise measurements are included demonstrating that the new model accurately fits widely different bias situations. A new model for mismatch offset in MOS transistors is presented, as a corollary of the flicker noise analysis. Finally, the correlation between flicker noise and mismatch offset, that can be seen as a DC noise, is shown. In chapter 4, the design of OTAs with an extended linear range, and very low transconductance, using series-parallel current division is presented. Precise tools are introduced for the estimation of noise and mismatch offset in series-parallel current mirrors, that are shown to help in the reduction of inaccuracies in the copy of currents with a large copy factor. The design and measurement of several OTA examples are presented. In chapter 5, the developed tools, and the OTAs shown, are employed in the design of the above mentioned filter for the piezoelectric accelerometer. A general methodology for the design of Gm-C filters with similar characteristics is established. The filter was fabricated and tested, successfully operating with a total power consumption of 233nA, up to a 2V power supply, with an input noise and mismatch offset of 2-4 Vrms, and 18 V respectively. To summarize the main results obtained were: The development of a new flicker noise model, the study of the effect of mismatch regarding series-parallel association, a new design methodology for OTAs and Gm-C filters. It is our hope that this constitutes a helpful set of tools for the circuit designer.En esta tesis se presenta un conjunto de herramientas para el diseño de circuitos integrados que implementan filtros transconductor-capacitor (Gm-C), de muy altas constantes de tiempo, con bajo ruido, y consumo de corriente por debajo del micro-Ampere. Como ejemplo de aplicación se toma un amplificador-pasabanda 2º orden, de ganancia 400 en la banda de 0.5 a 7Hz, que realiza el acondicionamiento de señal de un acelerómetro piezoeléctrico a ser empleado en un marcapasos implantable. El principal desafío es realizar en dicho filtro de tiempo continuo, muy altas constantes de tiempo sin usar componentes externos. La técnica elegida para alcanzar tal objetivo es la división serie-paralelo de corriente en transconductores (OTAs) simétricos estándar. Estos circuitos demostraron ser una excelente solución en cuanto al área ocupada, su consumo, ruido, linealidad, y en particular offset. Se diseñaron, fabricaron, y midieron, OTAs hasta 33pS -equivalente a una resistencia de 30G -, con hasta 1V de rango de lineal, y offset a la entrada de algunos mV, utilizando una tecnología CMOS de 0.8 micras de largo mínimo de canal. La aplicación requiere la asociación serie-paralelo de un gran número de transistores, y polarización con corrientes de hasta pico-Amperes, lo que constituye una situación poco frecuente en circuitos integrados analógicos. En este marco el diseñador debe elegir los modelos de transistor con sumo cuidado. Un aspecto central de esta tesis es también, el estudio y presentación de modelos adecuados de ruido y offset, que no resultan obvios al principio. En los primeros dos capítulos se realiza una introducción y se revisa, utilizando el modelo ACM, diferentes características del transistor MOS en función del nivel de inversión. En el capítulo 3 revisa la pertinencia y consistencia frente a la asociación serie-paralelo, de los modelos usuales de ruido de flicker o 1/f, y térmico. Luego se presenta, incluyendo medidas, un nuevo modelo físico, consistente, simple, y válido en todas las regiones de operación del transistor MOS, para el ruido de flicker. Como corolario a este estudio se presenta un nuevo modelo para estimar el desapareo entre transistores, en función no solo de la geometría, pero también de la polarización. Se demuestra la correlación, debido a su origen físico análogo, entre el ruido de flicker y el offset por desapareo que puede ser visto como un ruido en DC. En el capítulo 4 se presenta el diseño de OTAs con rango de linealidad extendido, y muy baja transconductancia, utilizando división serie-paralelo de corriente. Se presentan herramientas precisas para la estimación de offset y ruido y se demuestra la utilidad de la técnica para reducir el offset en espejos de corriente. Se presenta el diseño y medida de diversos OTAs. En el capítulo 5, las herramientas desarrolladas, y los OTAs presentados, son empleados en el diseño del filtro descripto para un acelerómetro piezoeléctrico. Se establece una metodología general para el diseño de filtros Gm-C con características similares. El filtro se fabricó y midió, operando en forma satisfactoria, con un consumo total de 230nA y hasta los 2V de tensión de alimentación, con ruido y offset a la entrada de tan solo 2-4 Vrms, y 18 V respectivamente. El desarrollo de un nuevo modelo de ruido 1/f para el transistor MOS, el estudio de la influencia del offset frente a la asociación serie-paralelo y su aplicación en OTAs, la metodología de diseño empleada, la demostración del uso de técnicas novedosas en una aplicación como la elegida que tiene relevancia tecnológica e interés académico; esperamos que todo ello constituya una contribución valiosa para la comunidad científica en microelectrónica y un conjunto de herramientas de utilidad para el diseño de circuitos

Information Power Efficiency Tradeoffs in Mixed Signal CMOS Circuits

Increasingly sensors for biological applications are implemented using mixed signal CMOS technologies. As feature sizes in modern technologies decrease with each generation, the power supply voltage also decreases, but the intrinsic noise level increases or remains the same. The performance of any sensor is quantified by the weakest detectable signal, and noise limits the ability of a sensor to detect the signal. In order to explore the trade-offs among incoming signal, the intrinsic physical noise of the circuit, and the available power resources, we apply basic concepts from information theory to CMOS circuits. In this work the circuits are modeled as communication channels with additive colored Gaussian noise and the signal transfer characteristics and noise properties are used to determine the classical Shannon capacity of the system. The waterfilling algorithm is applied to these circuits to obtain the information rate and the bit energy is subsequently calculated. In this dissertation we restricted our attention to operational transconductance amplifiers, a basic building block for many circuits and sensors and oftentimes a major source of noise in a sensor system. It is shown that for typical amplifiers the maximum information rate occurs at bandwidths above the dominant pole of the amplifier where the intrinsic physical circuit noise is diminished, but at the same time the output signal is attenuated. Thus these techniques suggest a methodology for the optimal use of the amplifier, but in many cases it is not practical to use an amplifier in this manner, that is at frequencies above its 3dB cutoff. Further, a direct consequence of applying the classic waterfilling algorithm leads to the idea of using modulation techniques to optimize system performance by shifting signals internally to higher frequencies, providing a practical means to achieve the information rates predicted by waterfilling and at the same time maintaining the real world application of these amplifiers. In addition, the information rates and bit energy for basic CMOS amplifier configurations are studied and compared across configurations and processes. Further the additional design constraints formed by adding the information rate and the bit energy to traditional design characteristics is explored

Programming of Floating-Gate Transistors for Nonvolatile Analog Memory Array

Since they were introduced, floating-gate (FG) transistors have been used as non-volatile digital memory. Recent research has shown that floating-gate transistors can be successfully used as analog memory, specifically as programmable voltage and current sources. However, their proliferation has been limited due to the complex programming procedure and the complex testing equipment. Analog applications such as field-programmable analog arrays (FPAAs) require hundreds to thousands of floating-gate transistors on a single chip which makes the programming process even more complicated and very challenging. Therefore, a simplified, compact, and low-power scheme to program FGs are necessary. This work presents an improved version of the typical methodology for FG programming. Additionally, a novel programming methodology that utilizes negative voltages is presented here. This method simplifies the programming process by eliminating the use of supplementary and complicated infrastructure circuits, which makes the FG transistor a good candidate for low-power wireless sensor nodes and portable systems

A collection of fuzzy logic-based tools for the automated design, modelling and test of analog circuits

We have developed a collection of tools for the design, modeling, and test of analog circuits. Sharing a common fuzzy-logic based framework, the tools are part of FASY (Fuzzy-Logic-Based Analog Synthesis), an analog design package developed at the University of Seville. The first tool uses fuzzy logic for topology selection of analog cells. It follows decision rules directly entered by a human expert or automatically generated from its experience with earlier designs. Second, a performance-modeling tool provides a qualitative description of a circuit's behavior. Alternatively, it can use a learning process to accurately model circuit performance. Finally, an analog testing tool uses a fuzzy-neuron classifier to detect and classify faults in analog circuits

An Ultra-Low-Power Track-and-Hold Amplifier

The future of electronics is the Internet of Things (IoT) paradigm, where always-on devices and sensors monitor and transform everyday life. A plethora of applications (such as navigating drivers past road hazards or monitoring bridge and building stresses) employ this technology. These unattended ground-sensor applications require decade(s)-long operational life-times without battery changes. Such electronics demand stringent performance specifications with only nano-Watt power levels.This thesis presents an ultra-low-power track-and-hold amplifier for such systems. It serves as the front-end of a SAR-ADC or the building block for equalizers or filters. This amplifier\u27s design attains exceptional hold times by mitigating switch subthreshold leakage and bulk leakage. Its novel transmission-gate topology achieves wide-swing performance. Though only consuming 100 pico-Watts, it achieves a precision of 7.6 effective number of bits (ENOB). The track-and-hold amplifier was designed in 130-nm CMOS

A Directly Matched PA-Integrated K-band Antenna for Efficient mm-Wave High-Power Generation

A K-band slot antenna element with integrated GaN (Gallium nitride) power amplifier (PA) is presented. It has been optimized through a circuit-EM co-design methodology to directly match the transistor drain output to its optimal load impedance (\ua0Zopt=17+j46Ω\ua0) while accounting for the over-the-air coupling effects in the vicinity of the transition between the PA and antenna. This obviates the need for using a potentially lossy and bandwidth-limiting output impedance matching network. The measured PA-integrated antenna gain of 15 dBi with a 40% total efficiency at 28 dBm output power agrees well with the theoretically achievable performance targets. The proposed element is compact (\ua00.6 70.5 70.3\ua0λ3\ua0), and thus well-suited to meet the high-performance demands of future emerging beamforming active antenna array applications

A Current-Mode Multi-Channel Integrating Analog-to-Digital Converter

Multi-channel analog to digital converters (ADCs) are required where signals from multiple sensors can be digitized. A lower power per channel for such systems is important in order that when the number of channels is increased the power does not increase drastically. Many applications require signals from current output sensors, such as photosensors and photodiodes to be digitized. Applications for these sensors include spectroscopy and imaging. The ability to digitize current signals without converting currents to voltages saves power, area, and the design time required to implement I-to-V converters. This work describes a novel and unique current-mode multi-channel integrating ADC which processes current signals from sensors and converts it to digital format. The ADC facilitates the processing of current analog signals without the use of transconductors. An attempt has been made also to incorporate voltage-mode techniques into the current-mode design so that the advantages of both techniques can be utilized to augment the performance of the system. Additionally since input signals are in the form of currents, the dynamic range of the ADC is less dependant on the supply voltage. A prototype 4-channel ADC design was fabricated in a 0.5-micron bulk CMOS process. The measurement results for a 10Ksps sampling rate include a DNL, which is less than 0.5 LSB, and a power consumption of less than 2mW per channel

A Monolithic Gm-C Filter based Very Low Power, Programmable, and Multi-Channel Harmonic Discrimination System using Analog Signal Processing

A highly selective monolithic band-pass filter with programmable characteristics at micro-power operation is presented. Very low power signal processing is of great interest in wireless sensing and Internet-of-Things applications. This filter enables long-term battery powered operation of a highly selective harmonic signal discriminator for an analog signal processing system. The Gm-C biquadratic circuits were fabricated in a 0.18-μm [micrometer] CMOS process. Each 2nd-order biquad filter nominally consumes 20 μW [microwatt] and can be programmed for the desired gain (0db3dB), quality factor (5 to 20), and center-frequency from 1kHz to 100kHz. The 8th-order filter channel achieved an effective quality factor of 30 at 100kHz with an overall power consumption of 108 μW