746 research outputs found

    Experimental study of artificial neural networks using a digital memristor simulator

    Get PDF
    © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a fully digital implementation of a memristor hardware simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field programmable gate array (FPGA) families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks (ANNs), implementing examples of associative memory and unsupervised learning of spatio-temporal correlations in parallel input streams using a simplified STDP. We provide the full circuit schematics of all our digital circuit designs and comment on the required hardware resources and their scaling trends, thus presenting a design framework for applications based on our hardware simulator.Peer ReviewedPostprint (author's final draft

    Abstract State Machines 1988-1998: Commented ASM Bibliography

    Get PDF
    An annotated bibliography of papers which deal with or use Abstract State Machines (ASMs), as of January 1998.Comment: Also maintained as a BibTeX file at http://www.eecs.umich.edu/gasm

    Circuit-level modelling and simulation of carbon nanotube devices

    No full text
    The growing academic interest in carbon nanotubes (CNTs) as a promising novel class of electronic materials has led to significant progress in the understanding of CNT physics including ballistic and non-ballistic electron transport characteristics. Together with the increasing amount of theoretical analysis and experimental studies into the properties of CNT transistors, the need for corresponding modelling techniques has also grown rapidly. This research is focused on the electron transport characteristics of CNT transistors, with the aim to develop efficient techniquesto model and simulate CNT devices for logic circuit analysis.The contributions of this research can be summarised as follows. Firstly, to accelerate the evaluation of the equations that model a CNT transistor, while maintaining high modelling accuracy, three efficient numerical techniques based on piece-wise linear, quadratic polynomial and cubic spline approximation have been developed. The numerical approximation simplifies the solution of the CNT transistor’s self-consistent voltage such that the calculation of the drain-source current is accelerated by at least two orders of magnitude. The numerical approach eliminates complicated calculations in the modelling process and facilitates the development of fast and efficient CNT transistor models for circuit simulation.Secondly, non-ballistic CNT transistors have been considered, and extended circuit-level models which can capture both ballistic and non-ballistic electron transport phenomena, including elastic scattering, phonon scattering, strain and tunnelling effects, have been developed. A salient feature of the developed models is their ability to incorporate both ballistic and non-ballistic transport mechanisms without a significant computational cost. The developed models have been extensively validated against reported transport theories of CNT transistors and experimental results.Thirdly, the proposed carbon nanotube transistor models have been implemented on several platforms. The underlying algorithms have been developed and tested in MATLAB, behaviourallevel models in VHDL-AMS, and improved circuit-level models have been implemented in two versions of the SPICE simulator. As the final contribution of this work, parameter variation analysis has been carried out in SPICE3 to study the performance of the proposed circuit-level CNT transistor models in logic circuit analysis. Typical circuits, including inverters and adders, have been analysed to determine the dependence of the circuit’s correct operation on CNT parameter variation

    A CO-SIMULATION ENVIRONMENT FOR MIXED SIGNAL, MULTI-DOMAIN SYSTEM LEVEL DESIGN EXPLORATION

    Get PDF
    This thesis presents a system-level co-simulation environment for mixed domain design exploration. By employing shared memory IPC (Inter-Process Communication) and utilizing PDES (Parallel Discrete Event Simulation) techniques, we examine two methods of synchronization, lock-step and dynamic. We then compare the performance of these two methods on a series of test systems as well as real designs using the Chatoyant MOEMS (Micro-Electro Mechanical Systems) simulator and the mixed HDL (Hardware Description Language) simulator from Model Technology, ModelSim. The results collected are used to ascertain which method provides the best overall performance with the least overhead

    A Software Toolchain for Physical System Description and Synthesis, and Applications to Microfluidic Design Automation

    Get PDF
    Microfluidic circuits are currently designed by hand, using a combination of the designer’s domain knowledge and educated intuition to determine unknown design parameters. As no microfluidic circuit design software exists to assist designers, circuits are typically tested by physically constructing them in silico and performing another design iteration should the prototype fail to operate correctly. Similar to how electronic design automation tools revolutionized the digital circuit design process, so too do microfluidic design packages have the potential to increase productivity for microfluidic circuit designers and allow more complex devices to be designed. Two of the primary software engineering problems to be solved in this space relate to design entry and design synthesis. First, the circuit designer requires a programming language to describe the behaviour and properties of the device they wish to build, and a compiler toolchain to convert this description into a model that can then be processed by other software tools. Second, once such a model is constructed, the remaining portions of the design toolchain must be constructed. It is necessary to implement software that can find unknown design parameters automatically to relieve the designer of much of the complexity that goes into creating such a circuit. Furthermore, automated testing and verification tools must be used to simulate the device and check for correctness and safety requirements before the engineer can have confidence in their design. In this thesis I outline work that has been done towards both of these goals. First, I describe a new programming language that has been developed for the purpose of describing and modelling physical systems, including but not limited to microfluidic circuits. This programming language, called “Manifold”, has been implemented following principles and features of modern functional programming languages, as well as drawing inspiration from VHDL and Verilog, the two industry-standard programming languages for EDA. The Manifold high-level language compiler carries out the process of translating a system description into a domain-agnostic intermediate representation. This representation is then passed to a domain-specific backend compiler which can perform further operations on the design, such as creating simulations, performing verification, and generating appropriate output products. Second, I perform a case study with respect to the creation of such a domain-specific backend for the domain of multi-phase microfluidic circuits. The process involved in taking a circuit description from design entry to device specification has a number of significant steps. I discuss in detail these steps with respect to the design of a multi-way droplet generator circuit. Such a circuit is difficult to design because of the behaviour of the key design parameter, the volume of generated droplets. The design goal is for each droplet generator on the device to produce droplets of a certain specified volume. However, the equation relating the properties of a droplet generator to the predicted droplet volume is complex and contains several nonlinearities, making it very difficult to solve by traditional methods. Recent advances in constraint solvers which can reason about nonlinear equations over real-valued terms make it possible to solve this equation efficiently for a given set of design constraints and goals, and produce many feasible specifications for droplet generators that meet the requirements. Another difficulty in designing these circuits is due to interactions between droplet generators. As the produced droplets have a significant hydrodynamic resistance, they affect the behaviour of the circuit by causing perturbations in the flow rates into the droplet generators. This has the potential to alter the volume of droplets that are being produced. Therefore, a means of regulating or controlling the flow rates must be found. I describe a potential solution in the form of a passive element analogous to a capacitor in an electrical circuit. Once an appropriate value for the capacitor is chosen, it remains to verify that it operates correctly under manufacturing variances in fabrication of the device. To perform this verification, a bounded model checker for real-valued differential equations is employed to demonstrate correctness or discover robustness issues. Furthermore, a simulation file for the MapleSim numerical simulation engine is generated in order to perform whole-design tests for further validation. The sequence in which these steps are performed closely follows the concept of “abstraction refinement” in formal methods, in which successively more detailed models are checked and a failure in one step can invoke a previous step with new information, allowing errors to be caught early and introducing the ability to iterate on the design. I describe such a refinement loop in place in the microfluidics backend that integrates these three steps in a coherent design flow, able to synthesize and verify many specifications for a microfluidic circuit, thereby automating a significant portion of the design process. The combination of the Manifold high-level language and microfluidics backend introduces a new design automation toolchain that demonstrates the effectiveness of constraint solvers in the tasks of design synthesis and verification. Further enhancements to the performance and capabilities of these solvers, as well as to the high-level language and backend, will in the future produce a general-purpose design package for microfluidic circuits that will allow for new, complex designs to be created and checked with confidence

    Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level

    Get PDF
    In recent technology nodes, reliability is considered a part of the standard design ¿ow at all levels of embedded system design. While techniques that use only low-level models at gate- and register transfer-level offer high accuracy, they are too inefficient to consider the overall application of the embedded system. Multi-level models with high abstraction are essential to efficiently evaluate the impact of physical defects on the system. This paper provides a methodology that leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This way it is possible to accurately evaluate the impact of the faults on the entire hardware/software system. A case study of a system consisting of hardware and software for image compression and data encryption is presented and the method is compared to a standard gate/RT mixed-level approac

    Delay-insensitive ternary logic (DITL)

    Get PDF
    This thesis focuses on development of a Single Rail Ternary Voltage Delay-Insensitive paradigm called Delay-Insensitive Ternary Logic (DITL), which is based on NULL Convention Logic (NCL). Single rail asynchronous logic has potential advantages over Dual-Rail logic such as reduction of Power and Interconnect as well as Logic Area. The DITL concept is developed in steps of individual circuit components. These components are designed at the transistor level and are connected together to form a registered pipeline system. Some variations in pipeline design are also investigated --Abstract, page iii

    Computer vision algorithms on reconfigurable logic arrays

    Full text link
    corecore