666 research outputs found
Increasing Flash Memory Lifetime by Dynamic Voltage Allocation for Constant Mutual Information
The read channel in Flash memory systems degrades over time because the
Fowler-Nordheim tunneling used to apply charge to the floating gate eventually
compromises the integrity of the cell because of tunnel oxide degradation.
While degradation is commonly measured in the number of program/erase cycles
experienced by a cell, the degradation is proportional to the number of
electrons forced into the floating gate and later released by the erasing
process. By managing the amount of charge written to the floating gate to
maintain a constant read-channel mutual information, Flash lifetime can be
extended. This paper proposes an overall system approach based on information
theory to extend the lifetime of a flash memory device. Using the instantaneous
storage capacity of a noisy flash memory channel, our approach allocates the
read voltage of flash cell dynamically as it wears out gradually over time. A
practical estimation of the instantaneous capacity is also proposed based on
soft information via multiple reads of the memory cells.Comment: 5 pages. 5 figure
Coding scheme for 3D vertical flash memory
Recently introduced 3D vertical flash memory is expected to be a disruptive
technology since it overcomes scaling challenges of conventional 2D planar
flash memory by stacking up cells in the vertical direction. However, 3D
vertical flash memory suffers from a new problem known as fast detrapping,
which is a rapid charge loss problem. In this paper, we propose a scheme to
compensate the effect of fast detrapping by intentional inter-cell interference
(ICI). In order to properly control the intentional ICI, our scheme relies on a
coding technique that incorporates the side information of fast detrapping
during the encoding stage. This technique is closely connected to the
well-known problem of coding in a memory with defective cells. Numerical
results show that the proposed scheme can effectively address the problem of
fast detrapping.Comment: 7 pages, 9 figures. accepted to ICC 2015. arXiv admin note: text
overlap with arXiv:1410.177
A Flexible BCH decoder for Flash Memory Systems using Cascaded BCH codes
NAND ash memories are widely used in consumer electronics, such as tablets, personal computers, smartphones, and gaming systems. However, unlike other standard storage devices, these ash memories suffer from various random errors. In order to address these reliability issues, various error correction codes (ECC) are employed. Bose-Chaudhuri Hocquenghem (BCH) code is the most common ECC used to address the errors in modern ash memories. Because of the limitation of the realization of the BCH codes for more extensive error correction, the modern ash memory devices use Low-density parity-check (LDPC) codes for error correction scheme. The realization of the LDPC decoders have greater complexity than BCH decoders, so these ECC decoders are implemented within the ash memory device. This thesis analyzes the limitation imposed by the state of the art implementation of BCH decoders and proposes a cascaded BCH code to address these limitations.
In order to support a variety of ash memory devices, there are three main challenges to be addressed for BCH decoders. First, the latency of the BCH decoders, in the case of no error scenario, should be less than 100us. Second, there should be flexibility in supporting different ECC block size; more precisely, the solution should be able to support 256, 512, 1024, and 2048 bytes of ECC block. Third, there should be flexibility in supporting different bit errors.
A recent development with Graphical Processing Units (GPUs) has attracted many researchers to use GPUs for non-graphical implementation. These GPUs are used in many consumer electronics as part of the system on chip (SOC) configuration. In this thesis we studied the limitation imposed by different implementations (VLSI, GPU, and CPU) of BCH decoders, and we propose a cascaded BCH code implemented using a hybrid approach to overcome the limitations of the BCH codes. By splitting the implementation across VLSI and GPUs, we have shown in this thesis that this method can provide flexibility over the block size and the bit error to be corrected
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