Oscillation-based DFT for Second-order Bandpass OTA-C Filters

This document is the Accepted Manuscript version. Under embargo until 6 September 2018. The final publication is available at Springer via https://doi.org/10.1007/s00034-017-0648-9.This paper describes a design for testability technique for second-order bandpass operational transconductance amplifier and capacitor filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. The proposed methodology converts filter under test into a quadrature oscillator using very simple techniques and measures the output frequency. Using feedback loops with nonlinear block, the filter-to-oscillator conversion techniques easily convert the bandpass OTA-C filter into an oscillator. With a minimum number of extra components, the proposed scheme requires a negligible area overhead. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of Tow-Thomas and KHN OTA-C filters. Simulation results in 0.25μm CMOS technology show that the proposed oscillation-based test strategy for OTA-C filters is suitable for catastrophic and parametric faults testing and also effective in detecting single and multiple faults with high fault coverage.Peer reviewedFinal Accepted Versio

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test methods

This work presents a case study, which attempts to improve the fault diagnosis and testability of the oscillation testing methodology applied to a typical two-stage CMOS operational amplifier. The proposed test method takes the advantage of good fault coverage through the use of a simple oscillation based test technique, which needs no test signal generation and combines it with quiescent supply current (IDDQ) testing to provide a fault confirmation. A built in current sensor (BICS), which introduces insignificant performance degradation of the circuit-under-test (CUT), has been utilized to monitor the power supply quiescent current changes in the CUT. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. The approach is attractive for its simplicity, robustness and capability of built-in-self test (BIST) implementation. It can also be generalized to the oscillation based test structures of other CMOS analog and mixed-signal integrated circuits. The practical results and simulations confirm the functionality of the proposed test method

Developing VLSI Curricula in Electrical and Computer Engineering Department

© ASEE 2010VLSI (Very Large Scale Integrated Circuits) technology has enabled the information technology revolution which greatly changed the life style of human society. Computers, internet, cellphones, digital cameras/camcorders and many other consumer electronic products are powered by VLSI technology. In the past decades, the VLSI industry was constantly driven by the miniaturization of transistors. As governed by Moore’s law, the number of transistors in the same chip area has been doubled every 12 to 18 months. Nowadays, a typical VLSI CPU chip can contain millions to billions of transistors. As a result, the design of VLSI system is becoming more and more complex. Various EDA tools must be used to help the design of modern VLSI chips. The semiconductor and VLSI industry remain strong needs for VLSI engineers each year. In this paper, efforts in developing systematic VLSI curricula in Electrical and Computer Engineering department have been proposed. The goal of the curricula is to prepare students to satisfy the growing demands of VLSI industry as well as the higher education/research institutions. Modern VLSI design needs a thorough understanding about VLSI in device, gate, module and system levels. We developed CPEG/EE 448D: Introduction to VLSI to give students a comprehensive introduction about digital VLSI design and analysis. In this course, various EDA tools (such as Mentor Graphics tools, Cadence PSPICE, Synopsys) are used in the course projects to help students practice the VLSI design. In addition, analog and mixed signal circuit design are becoming more and more important as MEMS (Microelectromechanical Systems) and Nano devices are integrated with VLSI into Systemon-Chip (SoC) design. We developed CPEG/EE 458: Analog VLSI to introduce the analog and mixed signal VLSI design. As portable electronics (e.g. laptops, cellphones, PDAs, digital cameras) becoming more and more popular, low power VLSI circuit design is becoming a hot field. We developed CPEG/EE 548: Low Power VLSI Circuit Design to introduce various low power techniques to reduce the power consumption of VLSI circuits. Nowadays the VLSI circuits can contain billions of transistors, the testing of such complex system becoming more and more challenging. We developed CPEG/EE 549: VLSI Testing to introduce various VLSI testing strategies for modern VLSI design. In addition to the design and testing, we also developed EE 448: Microelectronic Fabrication to introduce the fabrication processes of modern VLSI circuits. With such a series of VLSI related curricula, students have an opportunity to learn comprehensive knowledge and hands-on experience about VLSI circuit design, testing, fabrication and EDA tools. Students demonstrate tremendous interests in the VLSI field, and all the VLSI courses are generally oversubscripted by students in the early stage of enrollment. Many students are also doing the VLSI graduate research and published various papers/posters in the VLSI related journals/conferences

Power supply current [IPS] based testing of CMOS amplifier circuit with and without floating gate input transistors

This work presents a case study, which attempts to improve the fault diagnosis and testability of the power supply current based testing methodology applied to a typical two-stage CMOS operational amplifier and is extended to operational amplifier with floating gate input transistors*. The proposed test method takes the advantage of good fault coverage through the use of a simple power supply current measurement based test technique, which only needs an ac input stimulus at the input and no additional circuitry. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. In the present work, variations of ac ripple in the power supply current IPS, passing through VDD under the application of an ac input stimulus is measured to detect injected faults in the CMOS amplifier. The effect of parametric variation is taken into consideration by setting tolerance limit of ± 5% on the fault-free IPS value. The fault is identified if the power supply current, IPS falls outside the deviation given by the tolerance limit. This method presented can also be generalized to the test structures of other floating-gate MOS analog and mixed signal integrated circuits

On-line Testing Field Programmable Analog Array Circuits

This work presents an efficient methodology to on-line test field programmable analog array (FPAA) circuits. It proposes to partition the FPAA circuit under test into sub circuits. Each sub circuit is tested by replicating the sub circuit with programmable resources on FPAAs, and comparing the outputs of the original partitioned sub circuit and its replication. The advantages of this approach includes: low implementation cost, enhanced testability, and flexible testing schedules. This work also presents circuit techniques to address stability problems which are often encountered in the proposed on-line testing approach. In addition, the impact of performing circuit partition on testability is investigated in this work. It shows that testability is generally improved in partitioned circuits. Finally, experimental results are presented to demonstrate the feasibility and effectiveness of the proposed techniques

Programmable CMOS Analog-to-Digital Converter Design and Testability

In this work, a programmable second order oversampling CMOS delta-sigma analog-to-digital converter (ADC) design in 0.5µm n-well CMOS processes is presented for integration in sensor nodes for wireless sensor networks. The digital cascaded integrator comb (CIC) decimation filter is designed to operate at three different oversampling ratios of 16, 32 and 64 to give three different resolutions of 9, 12 and 14 bits, respectively which impact the power consumption of the sensor nodes. Since the major part of power consumed in the CIC decimator is by the integrators, an alternate design is introduced by inserting coder circuits and reusing the same integrators for different resolutions and oversampling ratios to reduce power consumption. The measured peak signal-to-noise ratio (SNR) for the designed second order delta-sigma modulator is 75.6dB at an oversampling ratio of 64, 62.3dB at an oversampling ratio of 32 and 45.3dB at an oversampling ratio of 16. The implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters is also presented. The BICS uses frequency as the output for fault detection in CUT. A fault is detected when the output frequency deviates more than ±10% from the reference frequency. The output frequencies of the BICS for various model parameters are simulated to check for the effect of process variation on the frequency deviation. A design for on-chip testability of CMOS ADC by linear ramp histogram technique using synchronous counter as register in code detection unit (CDU) is also presented. A brief overview of the histogram technique, the formulae used to calculate the ADC parameters, the design implemented in 0.5µm n-well CMOS process, the results and effectiveness of the design are described. Registers in this design are replaced by 6T-SRAM cells and a hardware optimized on-chip testability of CMOS ADC by linear ramp histogram technique using 6T-SRAM as register in CDU is presented. The on-chip linear ramp histogram technique can be seamlessly combined with ΔIDDQ technique for improved testability, increased fault coverage and reliable operation

Iddq testing of a CMOS 10-bit charge scaling digital-to-analog converter

This work presents an effective built-in current sensor (BICS), which has a very small impact on the performance of the circuit under test (CUT). The proposed BICS works in two-modes the normal mode and the test mode. In the normal mode the BICS is isolated from the CUT due to which there is no performance degradation of the CUT. In the testing mode, our BICS detects the abnormal current caused by permanent manufacturing defects. Further more our BICS can also distinguish the type of defect induced (Gate-source short, source-drain short and drain-gate short). Our BICS requires neither an external voltage source nor current source. Hence the BICS requires less area and is more efficient than the conventional current sensors. The circuit under test is a 10-bit digital to analog converter using charge-scaling architecture

Quiescent current testing of CMOS data converters

Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects. However, in sub-micron VLSI circuits, IDDQ is masked by the increased subthreshold (leakage) current of MOSFETs affecting the efficiency of I¬DDQ testing. In this work, an attempt has been made to perform robust IDDQ testing in presence of increased leakage current by suitably modifying some of the test methods normally used in industry. Digital CMOS integrated circuits have been tested successfully using IDDQ and IDDQ methods for physical defects. However, testing of analog circuits is still a problem due to variation in design from one specific application to other. The increased leakage current further complicates not only the design but also testing. Mixed-signal integrated circuits such as the data converters are even more difficult to test because both analog and digital functions are built on the same substrate. We have re-examined both IDDQ and IDDQ methods of testing digital CMOS VLSI circuits and added features to minimize the influence of leakage current. We have designed built-in current sensors (BICS) for on-chip testing of analog and mixed-signal integrated circuits. We have also combined quiescent current testing with oscillation and transient current test techniques to map large number of manufacturing defects on a chip. In testing, we have used a simple method of injecting faults simulating manufacturing defects invented in our VLSI research group. We present design and testing of analog and mixed-signal integrated circuits with on-chip BICS such as an operational amplifier, 12-bit charge scaling architecture based digital-to-analog converter (DAC), 12-bit recycling architecture based analog-to-digital converter (ADC) and operational amplifier with floating gate inputs. The designed circuits are fabricated in 0.5 μm and 1.5 μm n-well CMOS processes and tested. Experimentally observed results of the fabricated devices are compared with simulations from SPICE using MOS level 3 and BSIM3.1 model parameters for 1.5 μm and 0.5 μm n-well CMOS technologies, respectively. We have also explored the possibility of using noise in VLSI circuits for testing defects and present the method we have developed

Development of Test Procedure For CMOS Operational Amplifier Application Circuits

The integrated circuit (IC) is an ultra-small and fragile electrical system. A chip is basically an IC placed in a protective black plastic casing. The only contact the outside world has with the IC is through the chips input-output and power supply pins. ICs are also prone to damage and to locate damages inside a chip requires special probing techniques. These techniques are incorporated from the beginning of the design stage of a chip. Design for Testability (DFT) is a method applied to the design stage of chips such that electrical testing of the chips at the end of the production stage is greatly simplified. For a chip manufacturer, DFT helps cut production cost by shortening the time to test finished chips w hich eventually decreases the time to market the chip. Built-In Self Test (BIST) chips, an outcome of DFT, are ICs designed with extended circuitry dedicated to test its electrical behavior which eventually could inform a manufacturer w here damage has occurred. The testing circuitry inside a BIST chip is complimented by a test pattern, which is a special signal that executes the actual testing. The main objective of this study is to develop a test procedure to test CMOS Operational Amplifier (Op-Amp) application circuits. The focus in the development of the testing procedure is to find a suitable test pattern. The study conducted results in the success of developing the said test procedure. The development of the test procedure is aided by a powerful computer software from Tanner Research Inc. called Tanner Tools. It is used for circuit simulation and development of a mask layout for an Op-Amp. The major findings of this thesis is that a faulty Op-Amp application circuit behaves differently from a faultless Op-Amp application circuit. From this finding a test pattern can be derived by comparing between faulty and faultless Op-Amp application circuit behavior through simulation. The only disadvantage of the test pattern is that it could only detect damages in the Op-Amp if the damages occurs only one at any given time. Thus it can be argued that in relation to DFT for an Op-Amp application circuit, it is not impossible for damages to be pin-pointed using the developed procedure