Short Block-length Codes for Ultra-Reliable Low-Latency Communications

This paper reviews the state of the art channel coding techniques for ultra-reliable low latency communication (URLLC). The stringent requirements of URLLC services, such as ultra-high reliability and low latency, have made it the most challenging feature of the fifth generation (5G) mobile systems. The problem is even more challenging for the services beyond the 5G promise, such as tele-surgery and factory automation, which require latencies less than 1ms and failure rate as low as $10^{-9}$. The very low latency requirements of URLLC do not allow traditional approaches such as re-transmission to be used to increase the reliability. On the other hand, to guarantee the delay requirements, the block length needs to be small, so conventional channel codes, originally designed and optimised for moderate-to-long block-lengths, show notable deficiencies for short blocks. This paper provides an overview on channel coding techniques for short block lengths and compares them in terms of performance and complexity. Several important research directions are identified and discussed in more detail with several possible solutions.Comment: Accepted for publication in IEEE Communications Magazin

Configurable and Scalable Turbo Decoder for 4G Wireless Receivers

The increasing requirements of high data rates and quality of service (QoS) in fourth-generation (4G) wireless communication require the implementation of practical capacity approaching codes. In this chapter, the application of Turbo coding schemes that have recently been adopted in the IEEE 802.16e WiMax standard and 3GPP Long Term Evolution (LTE) standard are reviewed. In order to process several 4G wireless standards with a common hardware module, a reconfigurable and scalable Turbo decoder architecture is presented. A parallel Turbo decoding scheme with scalable parallelism tailored to the target throughput is applied to support high data rates in 4G applications. High-level decoding parallelism is achieved by employing contention-free interleavers. A multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. A new on-line address generation technique is introduced to support multiple Turbo interleaving patterns, which avoids the interleaver address memory that is typically necessary in the traditional designs. Design trade-offs in terms of area and power efficiency are analyzed for different parallelism and clock frequency goals

Deep Ensemble of Weighted Viterbi Decoders for Tail-Biting Convolutional Codes

Tail-biting convolutional codes extend the classical zero-termination convolutional codes: Both encoding schemes force the equality of start and end states, but under the tail-biting each state is a valid termination. This paper proposes a machine-learning approach to improve the state-of-the-art decoding of tail-biting codes, focusing on the widely employed short length regime as in the LTE standard. This standard also includes a CRC code. First, we parameterize the circular Viterbi algorithm, a baseline decoder that exploits the circular nature of the underlying trellis. An ensemble combines multiple such weighted decoders, each decoder specializes in decoding words from a specific region of the channel words' distribution. A region corresponds to a subset of termination states; the ensemble covers the entire states space. A non-learnable gating satisfies two goals: it filters easily decoded words and mitigates the overhead of executing multiple weighted decoders. The CRC criterion is employed to choose only a subset of experts for decoding purpose. Our method achieves FER improvement of up to 0.75dB over the CVA in the waterfall region for multiple code lengths, adding negligible computational complexity compared to the circular Viterbi algorithm in high SNRs

Information-Coupled Turbo Codes for LTE Systems

We propose a new class of information-coupled (IC) Turbo codes to improve the transport block (TB) error rate performance for long-term evolution (LTE) systems, while keeping the hybrid automatic repeat request protocol and the Turbo decoder for each code block (CB) unchanged. In the proposed codes, every two consecutive CBs in a TB are coupled together by sharing a few common information bits. We propose a feed-forward and feed-back decoding scheme and a windowed (WD) decoding scheme for decoding the whole TB by exploiting the coupled information between CBs. Both decoding schemes achieve a considerable signal-to-noise-ratio (SNR) gain compared to the LTE Turbo codes. We construct the extrinsic information transfer (EXIT) functions for the LTE Turbo codes and our proposed IC Turbo codes from the EXIT functions of underlying convolutional codes. An SNR gain upper bound of our proposed codes over the LTE Turbo codes is derived and calculated by the constructed EXIT charts. Numerical results show that the proposed codes achieve an SNR gain of 0.25 dB to 0.72 dB for various code parameters at a TB error rate level of $10^{-2}$, which complies with the derived SNR gain upper bound.Comment: 13 pages, 12 figure

Comparison between Different Channel Coding Techniques for IEEE 802.11be within Factory Automation Scenarios

This paper presents improvements in the physical layer reliability of the IEEE 802.11be standard. Most wireless system proposals do not fulfill the stringent requirements of Factory Automation use cases. The harsh propagation features of industrial environments usually require time retransmission techniques to guarantee link reliability. At the same time, retransmissions compromise latency. IEEE 802.11be, the upcoming WLAN standard, is being considered for Factory Automation (FA) communications. 802.11be addresses specifically latency and reliability difficulties, typical in the previous 802.11 standards. This paper evaluates different channel coding techniques potentially applicable in IEEE 802.11be. The methods suggested here are the following: WLAN LDPC, WLAN Convolutional Codes (CC), New Radio (NR) Polar, and Long Term Evolution (LTE)-based Turbo Codes. The tests consider an IEEE 802.11be prototype under the Additive White Gaussian Noise (AWGN) channel and industrial channel models. The results suggest that the best performing codes in factory automation cases are the WLAN LDPCs and New Radio Polar Codes.This work was supported in part by the Basque Government under Grant IT1234-19, in part by the PREDOC under Grant PRE2019_099407, and in part by the Spanish Government through project PHANTOM (MCIU/AEI/FEDER, UE) under Grant RTI2018-099162-B-I00

Multi-non-binary turbo codes

International audienceThis paper presents a new family of turbo codes called multi-non-binary turbo codes (MNBTCs) that generalizes the concept of turbo codes to multi-non-binary (MNB) parallel concatenated convolutional codes (PCCC). An MNBTC incorporates, as component encoders, recursive and systematic multi-non-binary convolutional encoders. The more compact data structure for these encoders confers some advantages on MNBTCs over other types of turbo codes, such as better asymptotic behavior, better convergence, and reduced latency. This paper presents in detail the structure and operation of an MNBTC: MNB encoding, trellis termination, Max-Log-MAP decoding adapted to the MNB case. It also shows an example of MNBTC whose performance is compared with the state-of-the-art turbo code adopted in the DVB-RCS2 standard

Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards

In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo codes with small resource overhead (less than 10%) compared to the single-mode architecture. To achieve high data rates in 4G, we present a parallel turbo decoder architecture with scalable parallelism tailored to the given throughput requirements. High-level parallelism is achieved by employing contention-free interleavers. Multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. We designed a very low-complexity recursive on-line address generator supporting multiple interleaving patterns, which avoids the interleaver address memory. Design trade-offs in terms of area and power efficiency are explored to find the optimal architectures. A 711 Mbps data rate is feasible with 32 Radix-4 MAP decoders running at 200 MHz clock rate.Texas Instruments Incorporate

Low latency parallel turbo decoding implementation for future terrestrial broadcasting systems

As a class of high-performance forward error correction codes, turbo codes, which can approach the channel capacity, could become a candidate of the coding methods in future terrestrial broadcasting (TB) systems. Among all the demands of future TB system, high throughput and low latency are two basic requirements that need to be met. Parallel turbo decoding is a very effective method to reduce the latency and improve the throughput in the decoding stage. In this paper, a parallel turbo decoder is designed and implemented in field-programmable gate array (FPGA). A reverse address generator is proposed to reduce the complexity of interleaver and also the iteration time. A practical method of modulo operation is realized in FPGA which can save computing resources compared with using division operation. The latency of parallel turbo decoder after implementation can be as low as 23.2 us at a clock rate of 250 MHz and the throughput can reach up to 6.92 Gbps