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Apparatus and method for congestion control in high speed networks
An adjustable bit rate (ABR) feedback control scheme is provided where the effects of multiloop delays and high priority traffic transmission are built into the control model. The data traffic is filtered by a low pass filter. Then, the low frequency bandwidth of the filtered traffic is measured and compared to a predetermined threshold. If the measured value exceeds the threshold, the ABR traffic flow is reduced. If the measured value is less than the threshold, the ABR traffic flow is increased. In addition, a General Prediction Control (GPC) method may be applied to the control model for optimal performance. An object of the invention is to minimize the unused link capacity subject to no congestion, where the ABR traffic is adapted to the low frequency variation of high priority traffic flow for high efficiency.Board of Regents, University of Texas Syste
Realization of a ROIC for 72x4 PV-IR detectors
Silicon Readout Integrated Circuits (ROIC) for HgCdTe Focal Plane Arrays of 1x4 and 72x4 photovoltaic detectors are represented. The analog circuit blocks are completely identical for both, while the digital control circuit is modified to
take into account the larger array size. The manufacturing technology is 0.35μm, double poly-Si, three-metal CMOS process. ROIC structure includes four elements TDI functioning with a super sampling rate of 3, bidirectional scanning, dead pixel de-selection, automatic gain adjustment in response to pixel deselection besides programmable four gain setting (up to 2.58pC storage), and programmable integration time. ROIC has four outputs with a dynamic range of 2.8V (from 1.2V to 4V) for an output load of 10pF capacitive in parallel with 1MΩ resistance, and operates at a clock frequency of 5 MHz. The input referred noise is less than 1037 μV with 460 fF integration capacitor, corresponding to 2978 electrons
The Outer Tracker Detector of the HERA-B Experiment. Part II: Front-End Electronics
The HERA-B Outer Tracker is a large detector with 112674 drift chamber
channels. It is exposed to a particle flux of up to 2x10^5/cm^2/s thus coping
with conditions similar to those expected for the LHC experiments. The
front-end readout system, based on the ASD-8 chip and a customized TDC chip, is
designed to fulfil the requirements on low noise, high sensitivity, rate
tolerance, and high integration density. The TDC system is based on an ASIC
which digitizes the time in bins of about 0.5 ns within a total of 256 bins.
The chip also comprises a pipeline to store data from 128 events which is
required for a deadtime-free trigger and data acquisition system. We report on
the development, installation, and commissioning of the front-end electronics,
including the grounding and noise suppression schemes, and discuss its
performance in the HERA-B experiment
A Framework for Differential Frame-Based Matching Algorithms in Input-Queued Switches
This article is made available under terms and conditions applicable to Open Access Policy Articl
Sprinklers: A Randomized Variable-Size Striping Approach to Reordering-Free Load-Balanced Switching
Internet traffic continues to grow exponentially, calling for switches that
can scale well in both size and speed. While load-balanced switches can achieve
such scalability, they suffer from a fundamental packet reordering problem.
Existing proposals either suffer from poor worst-case packet delays or require
sophisticated matching mechanisms. In this paper, we propose a new family of
stable load-balanced switches called "Sprinklers" that has comparable
implementation cost and performance as the baseline load-balanced switch, but
yet can guarantee packet ordering. The main idea is to force all packets within
the same virtual output queue (VOQ) to traverse the same "fat path" through the
switch, so that packet reordering cannot occur. At the core of Sprinklers are
two key innovations: a randomized way to determine the "fat path" for each VOQ,
and a way to determine its "fatness" roughly in proportion to the rate of the
VOQ. These innovations enable Sprinklers to achieve near-perfect load-balancing
under arbitrary admissible traffic. Proving this property rigorously using
novel worst-case large deviation techniques is another key contribution of this
work
Characterization of the Burst Stabilization Protocol for the RR/RR CICQ Switch
Input buffered switches with Virtual Output Queueing (VOQ) can be unstable
when presented with unbalanced loads. Existing scheduling algorithms, including
iSLIP for Input Queued (IQ) switches and Round Robin (RR) for Combined Input
and Crossbar Queued (CICQ) switches, exhibit instability for some schedulable
loads. We investigate the use of a queue length threshold and bursting
mechanism to achieve stability without requiring internal speed-up. An
analytical model is developed to prove that the burst stabilization protocol
achieves stability and to predict the minimum burst value needed as a function
of offered load. The analytical model is shown to have very good agreement with
simulation results. These results show the advantage of the RR/RR CICQ switch
as a contender for the next generation of high-speed switches.Comment: Presented at the 28th Annual IEEE Conference on Local Computer
Networks (LCN), Bonn/Konigswinter, Germany, Oct 20-24, 200
Design and stability analysis of high performance packet switches
With the rapid development of optical interconnection technology, high-performance packet switches are required to resolve contentions in a fast manner to satisfy the demand for high throughput and high speed rates. Combined input-crosspoint buffered (CICB) switches are an alternative to input-buffered (IB) packet switches to provide high-performance switching and to relax arbitration timing for packet switches with high-speed ports.
A maximum weight matching (MWM) scheme can provide 100% throughput under admissible traffic for lB switches. However, the high complexity of MWM prohibits its implementation in high-speed switches. In this dissertation, a feedback-based arbitration scheme for CICB switches is studied, where cell selection is based on the provided service to virtual output queues (VOQs). The feedback-based scheme is named round-robin with adaptable frame size (RR-AF) arbitration. The frame size in RR-AF is adaptably changed by the serviced and unserviced traffic. If a switch is stable, the switch provides 100% throughput. Here, it is proved that RR-AF can achieve 100% throughput under uniform admissible traffic.
Switches with crosspoint buffers need to consider the transmission delays, or round-trip times to define the crosspoint buffer size. As the buffered crossbar switch can be physically located far from the input ports, actual round-trip times can be non-negligible. To support non-negligible round-trip times in a buffered crossbar switch, the crosspoint buffer size needs to be increased. To satisfy this demand, this dissertation investigates how to select the crosspoint buffer size under non-negligible round trip times and under uniform traffic. With the analysis of stability margin, the relationship between the crosspoint buffer size and round-trip time is derived.
Considering that CICB switches deliver higher performance than lB switches and require no speedup, this dissertation investigates the maximum throughput performance that these switches can achieve. It is shown that CICB switches without speedup achieve 100% throughput under any admissible traffic through a fluid model. In addition, a new hybrid scheme, based on longest queue-first (as input arbitration) and longest column occupancy first (as output arbitration) is proposed, which achieves 100% throughput under uniform and non-uniform traffic patterns.
In order to give a better insight of the feedback nature of arbitration scheme for CICB switches, a frame-based round-robin arbitration scheme with explicit feedback control (FRE) is introduced. FRE dynamically sets the frame size according to the input load and to the accumulation of cells in a VOQ. FRE is used as the input arbitration scheme and it is combined with RR, PRR, and FRE as output arbitration schemes. These combined schemes deliver high performance under uniform and nonuniform traffic models using a buffered crossbar with one-cell crosspoint buffers. The novelty of FRE lies in that each VOQ sets the frame size by an adjustable parameter, Δ(i,j) which indicates the degree of service needed by VOQ(i, j). This value is adjusted according to the input loading and the accumulation of cells experienced in previous service cycles.
This dissertation also explores an analysis technique based on feedback control theory. This methodology is proposed to study the stability of arbitration and matching schemes for packet switches. A continuous system is used and a control model is used to emulate a queuing system. The technique is applied to a matching scheme. In addition, the study shows that the dwell time, which is defined as the time a queue receives service in a service opportunity, is a factor that affects the stability of a queuing system. This feedback control model is an alternative approach to evaluate the stability of arbitration and matching schemes
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