Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

High Current Matching over Full-Swing and Low-Glitch Charge Pump Circuit for PLLs

A high current matching over full-swing and low-glitch charge pump (CP) circuit is proposed. The current of the CP is split into two identical branches having one-half the original current. The two branches are connected in source-coupled structure, and a two-stage amplifier is used to regulate the common-source voltage for the minimum current mismatch. The proposed CP is designed in TSMC 0.18µm CMOS technology with a power supply of 1.8 V. SpectreRF based simulation results show the mismatch between the current source and the current sink is less than 0.1% while the current is 40 µA and output swing is 1.32 V ranging from 0.2 V to 1.52 V. Moreover, the transient output current presents nearly no glitches. The simulation results verify the usage of the CP in PLLs with the maximum tuning range from the voltage-controlled oscillator, as well as the low power supply applications

Architectures for RF Frequency synthesizers

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.\ud Written for:\ud Electrical and electronic engineer

Synchronization and Characterization of an Ultra-Short Laser for Photoemission and Electron-Beam Diagnostics Studies at a Radio Frequency Photoinjector

A commercially-available titanium-sapphire laser system has recently been installed at the Fermilab A0 photoinjector laboratory in support of photoemission and electron beam diagnostics studies. The laser system is synchronized to both the 1.3-GHz master oscillator and a 1-Hz signal use to trigger the radiofrequency system and instrumentation acquisition. The synchronization scheme and performance are detailed. Long-term temporal and intensity drifts are identified and actively suppressed to within 1 ps and 1.5%, respectively. Measurement and optimization of the laser's temporal profile are accomplished using frequency-resolved optical gating.Comment: 16 pages, 17 figures, Preprint submitted to Elsevie

Solving the Jitter Problem in Microwave Compressed Ultrafast Electron Diffraction Instruments: Robust Sub-50 fs Cavity-Laser Phase Stabilization

We demonstrate the compression of electron pulses in a high-brightness ultrafast electron diffraction (UED) instrument using phase-locked microwave signals directly generated from a mode-locked femtosecond oscillator. Additionally, a continuous-wave phase stabilization system that accurately corrects for phase fluctuations arising in the compression cavity from both power amplification and thermal drift induced detuning was designed and implemented. An improvement in the microwave timing stability from 100 fs to 5 fs RMS is measured electronically and the long-term arrival time stability ($>$10 hours) of the electron pulses improves to below our measurement resolution of 50 fs. These results demonstrate sub-relativistic ultrafast electron diffraction with compressed pulses that is no longer limited by laser-microwave synchronization.Comment: Accepted for publication in Structural Dynamic

Nonlinear dynamics of a solid-state laser with injection

We analyze the dynamics of a solid-state laser driven by an injected sinusoidal field. For this type of laser, the cavity round-trip time is much shorter than its fluorescence time, yielding a dimensionless ratio of time scales $\sigma \ll 1$. Analytical criteria are derived for the existence, stability, and bifurcations of phase-locked states. We find three distinct unlocking mechanisms. First, if the dimensionless detuning $\Delta$ and injection strength $k$ are small in the sense that $k = O(\Delta) \ll \sigma^{1/2}$, unlocking occurs by a saddle-node infinite-period bifurcation. This is the classic unlocking mechanism governed by the Adler equation: after unlocking occurs, the phases of the drive and the laser drift apart monotonically. The second mechanism occurs if the detuning and the drive strength are large: $k =O(\Delta) \gg \sigma^{1/2}$. In this regime, unlocking is caused instead by a supercritical Hopf bifurcation, leading first to phase trapping and only then to phase drift as the drive is decreased. The third and most interesting mechanism occurs in the distinguished intermediate regime $k, \Delta = O(\sigma^{1/2})$. Here the system exhibits complicated, but nonchaotic, behavior. Furthermore, as the drive decreases below the unlocking threshold, numerical simulations predict a novel self-similar sequence of bifurcations whose details are not yet understood.Comment: 29 pages in revtex + 8 figs in eps. To appear in Phys. Rev. E (scheduled tentatively for the issue of 1 Oct 98