Synthesis and Optimization of Reversible Circuits - A Survey

Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms --- search-based, cycle-based, transformation-based, and BDD-based --- as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table

Scrambling speed of random quantum circuits

Random transformations are typically good at "scrambling" information. Specifically, in the quantum setting, scrambling usually refers to the process of mapping most initial pure product states under a unitary transformation to states which are macroscopically entangled, in the sense of being close to completely mixed on most subsystems containing a fraction fn of all n particles for some constant f. While the term scrambling is used in the context of the black hole information paradox, scrambling is related to problems involving decoupling in general, and to the question of how large isolated many-body systems reach local thermal equilibrium under their own unitary dynamics. Here, we study the speed at which various notions of scrambling/decoupling occur in a simplified but natural model of random two-particle interactions: random quantum circuits. For a circuit representing the dynamics generated by a local Hamiltonian, the depth of the circuit corresponds to time. Thus, we consider the depth of these circuits and we are typically interested in what can be done in a depth that is sublinear or even logarithmic in the size of the system. We resolve an outstanding conjecture raised in the context of the black hole information paradox with respect to the depth at which a typical quantum circuit generates an entanglement assisted encoding against the erasure channel. In addition, we prove that typical quantum circuits of poly(log n) depth satisfy a stronger notion of scrambling and can be used to encode alpha n qubits into n qubits so that up to beta n errors can be corrected, for some constants alpha, beta > 0.Comment: 24 pages, 2 figures. Superseded by http://arxiv.org/abs/1307.063

Analysis and application of digital spectral warping in analog and mixed-signal testing

Spectral warping is a digital signal processing transform which shifts the frequencies contained within a signal along the frequency axis. The Fourier transform coefficients of a warped signal correspond to frequency-domain 'samples' of the original signal which are unevenly spaced along the frequency axis. This property allows the technique to be efficiently used for DSP-based analog and mixed-signal testing. The analysis and application of spectral warping for test signal generation, response analysis, filter design, frequency response evaluation, etc. are discussed in this paper along with examples of the software and hardware implementation

Overview of Hydra: a concurrent language for synchronous digital circuit design

Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit specification. The design language is inherently concurrent, and it offers black box abstraction and general design patterns that simplify the design of circuits with regular structure. Hydra specifications are concise, allowing the complete design of a computer system as a digital circuit within a few pages. This paper discusses the motivations behind Hydra, and illustrates the system with a significant portion of the design of a basic RISC processor