9,796 research outputs found
Design and Characterization of Crossbar architecture Velostat-based Flexible Writing Pad
Pressure sensors are popular in a large variety of industries. For some
applications, it is critical for these sensors to come in a flexible form
factor. With the development of new synthetic polymers and novel fabrication
techniques, flexible pressure sensing arrays are more easily accessible and can
serve a variety of applications. As part of this dissertation, we demonstrate
one such application of the same by developing a low-cost flexible writing pad
and doing crosstalk analysis on sensors with similar working principles. We
present a low-cost, flexible writing pad that uses a 16x16 pressure sensing
matrix based on the piezoresistive thin film of velostat. The writing area is 5
cm x 5 cm with an effective pixel area of 0.06 mm^2. A read-out circuit is
designed to detect the change in resistance of the velostat pixel using a
voltage divider. A microprocessor raster scans through the sensor pixel matrix
to obtain a data frame of 256 numbers. This data is processed using techniques
like squaring and normalising (S\&N), Gaussian blurring, and adaptive
thresholding to generate a more readable output. The writing pad is able to
resolve characters larger than 2 cm in length. The flexible writing pad
produces legible output while flexed at a bending radius of up to 4 cm. Such
flexibility promises to enhance the usability and portability of the writing
pad significantly. We noticed that the raw data produced by the writing pad had
a lot of crosstalk which we were subsequently able to resolve using the
algorithms mentioned above. Such crosstalk has been reported in literature
multiple times and is common, especially for sensors of the crossbar
architecture.Crosstalk, in a sensor matrix, is the unwanted signal obtained at
a sensor pixel that is not directly related to the stimulus. This paper
presents a novel approach towards quantifying the crosstalk characteristics of
a sensor matrix
Beam scanning by liquid-crystal biasing in a modified SIW structure
A fixed-frequency beam-scanning 1D antenna based on Liquid Crystals (LCs) is designed for application in 2D scanning with lateral alignment. The 2D array environment imposes full decoupling of adjacent 1D antennas, which often conflicts with the LC requirement of DC biasing: the proposed design accommodates both. The LC medium is placed inside a Substrate Integrated Waveguide (SIW) modified to work as a Groove Gap Waveguide, with radiating slots etched on the upper broad wall, that radiates as a Leaky-Wave Antenna (LWA). This allows effective application of the DC bias voltage needed for tuning the LCs. At the same time, the RF field remains laterally confined, enabling the possibility to lay several antennas in parallel and achieve 2D beam scanning. The design is validated by simulation employing the actual properties of a commercial LC medium
Study of neural circuits using multielectrode arrays in movement disorders
Treballs Finals de Grau d'Enginyeria Biomèdica. Facultat de Medicina i Ciències de la Salut. Universitat de Barcelona. Curs: 2022-2023. Tutor/Director: RodrÃguez Allué, Manuel JoséNeurodegenerative movement-related disorders are characterized by a progressive degeneration and loss of neurons, which lead to motor control impairment. Although the precise mechanisms underlying these conditions are still unknown, an increasing number of studies point towards the analysis of neural networks and functional connectivity to unravel novel insights. The main objective of this work is to understand cellular mechanisms related to dysregulated motor control symptoms in movement disorders, such as Chorea-Acanthocytosis (ChAc), by employing multielectrode arrays to analyze the electrical activity of neuronal networks in mouse models. We found no notable differences in cell viability between neurons with and without VPS13A knockdown, that is the only gene known to be implicated in the disease, suggesting that the absence of VPS13A in neurons may be partially compensated by other proteins. The MEA setup used to capture the electrical activity from neuron primary cultures is described in detail, pointing out its specific characteristics. At last, we present the alternative backup approach implemented to overcome the challenges faced during the research process and to explore the advanced algorithms for signal processing and analysis.
In this report, we present a thorough account of the conception and implementation of our research, outlining the multiple limitations that have been encountered all along the course of the project. We provide a detailed analysis on the project’s economical and technical feasibility, as well as a comprehensive overview of the ethical and legal aspects considered during the execution
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Serial Biasing Technique for Rapid Single Flux Quantum Circuits
Superconductor electronics based on the Single Flux Quantum (SFQ) technology are considered a strong contender for the ‘beyond CMOS’ future of digital circuits because of the high speed and low power dissipation associated with them. In fact, digital operations beyond tens of GHz have been routinely demonstrated in the SFQ technology. These circuits have widespread applications such as high-speed analog-to-digital conversion, digital signal processing, high speed computing and in emerging topics such as control circuitry for superconducting quantum computing.
Rapid Single Flux Quantum (RSFQ) circuits have emerged as a promising candidate within the SFQ technology, with information encoded in picosecond wide, milli-volt voltage pulses. As is the case with any integrated circuit technology, scalability of RSFQ circuits is essential to realizing their applications. These circuits, based on the Josephson junction, require a DC bias current for the correct operation. The DC bias current requirement increases with circuit complexity, and this has multiple implications on circuit operation. Large currents produce magnetic fields that can interfere with logic operation. Furthermore, the heat load delivered to the superconducting chip also increases with current which could result in the circuit becoming ‘normal’ and not superconducting. These problems make reduction of the bias current necessary.
Serial Biasing (SB) is a bias current reduction technique, that has been proposed in the past. In this technique, a digital circuit is partitioned into multiple identical islands and bias current is provided to each island in a serial manner. While this scheme is promising, there are multiple challenges such as design of the driver-receiver pair circuit resulting in robust and wide operating bias margins, current management on the floating islands, etc.
This thesis investigates SB in a systematic manner, focusing on the design and measurement of the fundamental components of this technique with an emphasis on reliability and scalability. It presents works on circuit techniques achieving high speed serially biased RSFQ circuits with robust operating margins and the experimental evidence to support the ideas. It develops a framework for serial biasing that could be used by electronic design tools to automate design and synthesis of complex RSFQ circuits. It also investigates Passive Transmission Lines (PTLs) for use as passive interconnects between library cells in a complex design, reducing the DC bias current required by the active circuitry
Meso-scale FDM material layout design strategies under manufacturability constraints and fracture conditions
In the manufacturability-driven design (MDD) perspective, manufacturability of the product or system is the most important of the design requirements. In addition to being able to ensure that complex designs (e.g., topology optimization) are manufacturable with a given process or process family, MDD also helps mechanical designers to take advantage of unique process-material effects generated during manufacturing. One of the most recognizable examples of this comes from the scanning-type family of additive manufacturing (AM) processes; the most notable and familiar member of this family is the fused deposition modeling (FDM) or fused filament fabrication (FFF) process. This process works by selectively depositing uniform, approximately isotropic beads or elements of molten thermoplastic material (typically structural engineering plastics) in a series of pre-specified traces to build each layer of the part. There are many interesting 2-D and 3-D mechanical design problems that can be explored by designing the layout of these elements. The resulting structured, hierarchical material (which is both manufacturable and customized layer-by-layer within the limits of the process and material) can be defined as a manufacturing process-driven structured material (MPDSM). This dissertation explores several practical methods for designing these element layouts for 2-D and 3-D meso-scale mechanical problems, focusing ultimately on design-for-fracture. Three different fracture conditions are explored: (1) cases where a crack must be prevented or stopped, (2) cases where the crack must be encouraged or accelerated, and (3) cases where cracks must grow in a simple pre-determined pattern. Several new design tools, including a mapping method for the FDM manufacturability constraints, three major literature reviews, the collection, organization, and analysis of several large (qualitative and quantitative) multi-scale datasets on the fracture behavior of FDM-processed materials, some new experimental equipment, and the refinement of a fast and simple g-code generator based on commercially-available software, were developed and refined to support the design of MPDSMs under fracture conditions. The refined design method and rules were experimentally validated using a series of case studies (involving both design and physical testing of the designs) at the end of the dissertation. Finally, a simple design guide for practicing engineers who are not experts in advanced solid mechanics nor process-tailored materials was developed from the results of this project.U of I OnlyAuthor's request
Capacitor Optimization in Power Distribution Networks Using Numerical Computation Techniques
This paper presents a power distribution network (PDN) decoupling capacitor
optimization application with three primary goals: reduction of solution times
for large networks, development of flexible network scoring routines, and a
concentration strictly on achieving the best network performance. Example
optimizations are performed using broadband models of a printed circuit board
(PCB), a chip-package, on-die networks, and candidate capacitors. A novel
worst-case time-domain optimization technique is presented as an alternative to
the traditional frequency-domain approach. The trade-offs and criteria for
scoring the computed network are presented. The output is a recommended set of
capacitors which can then be applied to the product design.Comment: 24 pages, 13 figures, DesignCon 202
Intelligent computing : the latest advances, challenges and future
Computing is a critical driving force in the development of human civilization. In recent years, we have witnessed the emergence of intelligent computing, a new computing paradigm that is reshaping traditional computing and promoting digital revolution in the era of big data, artificial intelligence and internet-of-things with new computing theories, architectures, methods, systems, and applications. Intelligent computing has greatly broadened the scope of computing, extending it from traditional computing on data to increasingly diverse computing paradigms such as perceptual intelligence, cognitive intelligence, autonomous intelligence, and human computer fusion intelligence. Intelligence and computing have undergone paths of different evolution and development for a long time but have become increasingly intertwined in recent years: intelligent computing is not only intelligence-oriented but also intelligence-driven. Such cross-fertilization has prompted the emergence and rapid advancement of intelligent computing
Non-equilibrium VLS-grown stable ST12-Ge thin film on Si substrate: A study on strain-induced band-engineering
The current work describes a novel method of growing thin films of stable
crystalline ST12-Ge, a high pressure polymorph of Ge, on Si substrate by a
non-equilibrium VLS-technique. The study explores the scheme of band
engineering of ST12-Ge by inducing process-stress into it as a function of the
growth temperature and film thickness. In the present work, ST12-Ge films are
grown at 180 C - 250 C to obtain thicknesses of ~4.5-7.5 nm, which possess
extremely good thermal stability up to a temperature of ~350 C. Micro-Raman
study shows the stress induced in such ST12-Ge films to be compressive in
nature and vary in the range of ~0.5-7.5 GPa. The measured direct band gap is
observed to vary within 0.688 eV to 0.711 eV for such stresses, and four
indirect band gaps are obtained to be 0.583 eV, 0.614-0.628 eV, 0.622-0.63 eV
and 0.623-0.632 eV, accordingly. The corresponding band structures for
unstrained and strained ST12-Ge are calculated by performing DFT simulation,
which shows that a compressive stress transforms the fundamental band gap at
M-G valley from indirect to direct one. Henceforth, the possible route of
strain induced band engineering in ST12-Ge is explored by analyzing all the
transitions in strained and unstrained band structures along with
substantiation of the experimental results and theoretical calculations. The
investigation shows that unstrained ST12-Ge is a natural n-type semiconductor
which transforms into p-type upon incorporation of a compressive stress of ~5
GPa, with the in-plane electron effective mass components at M-G band edge to
be ~0.09 me. Therefore, such band engineered ST12-Ge exhibits superior mobility
along with its thermal stability and compatibility with Si, which can have
potential applications to develop high-speed MOS devices for advanced CMOS
technology
It is too hot in here! A performance, energy and heat aware scheduler for Asymmetric multiprocessing processors in embedded systems.
Modern architecture present in self-power devices such as mobiles or tablet computers proposes the use of asymmetric processors that allow either energy-efficient or performant computation on the same SoC. For energy efficiency and performance consideration, the asymmetry resides in differences in CPU micro-architecture design and results in diverging raw computing capability. Other components such as the processor memory subsystem also show differences resulting in different memory transaction timing. Moreover, based on a bus-snoop protocol, cache coherency between processors comes with a peculiarity in memory latency depending on the processors operating frequencies. All these differences come with challenging decisions on both application schedulability and processor operating frequencies. In addition, because of the small form factor of such embedded systems, these devices generally cannot afford active cooling systems. Therefore thermal mitigation relies on dynamic software solutions. Current operating systems for embedded systems such as Linux or Android do not consider all these particularities. As such, they often fail to satisfy user expectations of a powerful device with long battery life. To remedy this situation, this thesis proposes a unified approach to deliver high-performance and energy-efficiency computation in each of its flavours, considering the memory subsystem and all computation units available in the system. Performance is maximized even when the device is under heavy thermal constraints. The proposed unified solution is based on accurate models targeting both performance and thermal behaviour and resides at the operating systems kernel level to manage all running applications in a global manner. Particularly, the performance model considers both the computation part and also the memory subsystem of symmetric or asymmetric processors present in embedded devices. The thermal model relies on the accurate physical thermal properties of the device. Using these models, application schedulability and processor frequency scaling decisions to either maximize performance or energy efficiency within a thermal budget are extensively studied. To cover a large range of application behaviour, both models are built and designed using a generative workload that considers fine-grain details of the underlying microarchitecture of the SoC. Therefore, this approach can be derived and applied to multiple devices with little effort. Extended evaluation on real-world benchmarks for high performance and general computing, as well as common applications targeting the mobile and tablet market, show the accuracy and completeness of models used in this unified approach to deliver high performance and energy efficiency under high thermal constraints for embedded devices
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