Proportional-Integral Degradation (PI-Deg) control allows accurate tracking of biomolecular concentrations with fewer chemical reactions

We consider the design of synthetic embedded feedback circuits that can implement desired changes in the concentration of the output of a biomolecular process (reference tracking in control terminology). Such systems require the use of a "subtractor", to generate an error signal that captures the difference between the current and desired value of the process output. Unfortunately, standard implementations of the subtraction operator using chemical reaction networks are one-sided, i.e. they cannot produce negative error signals. Previous attempts to deal with this problem by representing signals as the difference in concentrations of two different biomolecular species lead to a doubling of the number of chemical reactions required to generate the circuit, hence sharply increasing the difficulty of experimental implementations and limiting the complexity of potential designs. Here we propose an alternative approach that introduces a degradation term into the classical proportion-integral control scheme. The extra tuning flexibility of the resulting PI-Deg controller compensates for the limitations of the one-sided subtraction operator, providing robust high-performance tracking of concentration changes with a minimal number of chemical reactions

Design of an embedded inverse-feedforward biomolecular trackingcontroller for enzymatic reaction processes

Feedback control is widely used in chemical engineering to improve the performance and robustness of chemical processes. Feedback controllers require a ‘subtractor’ that is able to compute the error between the process output and the reference signal. In the case of embedded biomolecular control circuits, subtractors designed using standard chemical reaction network theory can only realise one-sided subtraction, rendering standard controller design approaches inadequate. Here, we show how a biomolecular controller that allows tracking of required changes in the outputs of enzymatic reaction processes can be designed and implemented within the framework of chemical reaction network theory. The controller architecture employs an inversion-based feedforward controller that compensates for the limitations of the one-sided subtractor that generates the error signals for a feedback controller. The proposed approach requires significantly fewer chemical reactions to implement than alternative designs, and should have wide applicability throughout the fields of synthetic biology and biological engineering

Robustness analysis of a nucleic acid controller for a dynamic biomolecular process using the structured singular value

In the field of synthetic biology, theoretical frameworks and software tools are now available that allow control systems represented as chemical reaction networks to be translated directly into nucleic acid-based chemistry, and hence implement embedded control circuitry for biomolecular processes. However, the development of tools for analysing the robustness of such controllers is still in its infancy. An interesting feature of such control circuits is that, although the transfer function of a linear system can be easily implemented via a chemical network of catalysis, degradation and annihilation reactions, this introduces additional nonlinear dynamics, due to the annihilation kinetics. We exemplify this problem for a dynamical biomolecular feedback system, and demonstrate how the structured singular value (μ) analysis framework can be extended to rigorously analyse the robustness of this class of system. We show that parametric uncertainty in the system affects the location of its equilibrium, and that this must be taken into account in the analysis. We also show that the parameterisation of the system can be scaled for experimental feasibility without affecting its robustness properties, and that a statistical analysis via Monte Carlo simulation fails to uncover the worst-case uncertainty combination found by μ-analysis.</p

VLSI Design of Heart Model

Heart disease is a leading cause of death in the United States and abroad. Research interests arise in understanding the nature of the dynamics of the heart and seeking methods to control and suppress arrhythmias. Simulation of the heart electrical activity is a useful approach to study the heart because it yields some quantities of interest that cannot practically be obtained in any other way. However, the complexity of the human heart leads to complicated mathematical models, and consequently, modeling arrhythmias of a whole heart with computers is extremely data intensive and computational challenging. In this dissertation, we introduce an analog VLSI design that simulates cardiac electrical activities. The selected cardiac model is based on the Beeler-Reuter equations and the continuous core-conductor model. The Beeler-Reuter equations formulate the membrane ionic kinetics of ventricular cells, and the core-conductor model describes the electrical signal conduction on cardiac tissues. We discuss the design flows of mapping equations into circuits and present a set of circuit blocks of basic mathematical function units. The transistor circuits for realizing the ionic model of a single cell is introduced, and capacitors are used to calculate time directives. A method of shifting the initial conditions of differential equations to zero is discussed for saving the circuit which sets up the initial voltages of the capacitors. We also introduce a method of implementing reaction-diffusion systems using non-linear RC networks, and present the circuit which simulates the reaction-diffusion process, i.e. the electrical propagation, of the heart. Error analysis is carried out for the circuit-realized Beeler-Reuter model by comparing the simulated functions with the equation calculated values. The PSpice simulation results show that the circuit created action potential is satisfactory. The important reentry phenomena, the primary mechanism underlying fibrillation, is presented, and an anatomical reentry in the 1-dimensional model and a functional reentry (spiral wave) in the 2-dimensional model are successfully simulated in circuits. The presented methods of implementing equations with analog VLSI circuit contribute to the fundamentals for a novel technique of obtaining numerical solutions and potential fast application-specified analog computational devices if the circuits are fabricated on chips. Unlike computing with digital computers, which is mainly a serial process and needs to discretize the space and the time domain for finding numerical solutions of the discretization points one by one, computation with analog VLSI relies on the physics of the electrical devices and takes advantage of the integration properties of capacitors and, hence, computing in analog circuit hardware is a parallel process and can be real-time, that is, the calculation time is the time simulated by equations

Autonomously Reconfigurable Artificial Neural Network on a Chip

Artificial neural network (ANN), an established bio-inspired computing paradigm, has proved very effective in a variety of real-world problems and particularly useful for various emerging biomedical applications using specialized ANN hardware. Unfortunately, these ANN-based systems are increasingly vulnerable to both transient and permanent faults due to unrelenting advances in CMOS technology scaling, which sometimes can be catastrophic. The considerable resource and energy consumption and the lack of dynamic adaptability make conventional fault-tolerant techniques unsuitable for future portable medical solutions. Inspired by the self-healing and self-recovery mechanisms of human nervous system, this research seeks to address reliability issues of ANN-based hardware by proposing an Autonomously Reconfigurable Artificial Neural Network (ARANN) architectural framework. Leveraging the homogeneous structural characteristics of neural networks, ARANN is capable of adapting its structures and operations, both algorithmically and microarchitecturally, to react to unexpected neuron failures. Specifically, we propose three key techniques --- Distributed ANN, Decoupled Virtual-to-Physical Neuron Mapping, and Dual-Layer Synchronization --- to achieve cost-effective structural adaptation and ensure accurate system recovery. Moreover, an ARANN-enabled self-optimizing workflow is presented to adaptively explore a "Pareto-optimal" neural network structure for a given application, on the fly. Implemented and demonstrated on a Virtex-5 FPGA, ARANN can cover and adapt 93% chip area (neurons) with less than 1% chip overhead and O(n) reconfiguration latency. A detailed performance analysis has been completed based on various recovery scenarios

Combined mechanistic modeling and machine-learning approaches in systems biology - A systematic literature review

Background and objective: Mechanistic-based Model simulations (MM) are an effective approach commonly employed, for research and learning purposes, to better investigate and understand the inherent behavior of biological systems. Recent advancements in modern technologies and the large availability of omics data allowed the application of Machine Learning (ML) techniques to different research fields, including systems biology. However, the availability of information regarding the analyzed biological context, sufficient experimental data, as well as the degree of computational complexity, represent some of the issues that both MMs and ML techniques could present individually. For this reason, recently, several studies suggest overcoming or significantly reducing these drawbacks by combining the above-mentioned two methods. In the wake of the growing interest in this hybrid analysis approach, with the present review, we want to systematically investigate the studies available in the scientific literature in which both MMs and ML have been combined to explain biological processes at genomics, proteomics, and metabolomics levels, or the behavior of entire cellular populations. Methods: Elsevier Scopus®, Clarivate Web of Science™ and National Library of Medicine PubMed® databases were enquired using the queries reported in Table 1, resulting in 350 scientific articles. Results: Only 14 of the 350 documents returned by the comprehensive search conducted on the three major online databases met our search criteria, i.e. present a hybrid approach consisting of the synergistic combination of MMs and ML to treat a particular aspect of systems biology. Conclusions: Despite the recent interest in this methodology, from a careful analysis of the selected papers, it emerged how examples of integration between MMs and ML are already present in systems biology, highlighting the great potential of this hybrid approach to both at micro and macro biological scales

Spiking Neural Networks models targeted for implementation on Reconfigurable Hardware

La tesis presentada se centra en la denominada tercera generación de redes neuronales artificiales, las Redes Neuronales Spiking (SNN) también llamadas ‘de espigas’ o ‘de eventos’. Este campo de investigación se convirtió en un tema popular e importante en la última década debido al progreso de la neurociencia computacional. Las Redes Neuronales Spiking, que tienen no sólo la plasticidad espacial sino también temporal, ofrecen una alternativa prometedora a las redes neuronales artificiales clásicas (ANN) y están más cerca de la operación real de las neuronas biológicas ya que la información se codifica y transmite usando múltiples espigas o eventos en forma de trenes de pulsos. Este campo ha ido creciendo en los últimos años y ampliado el área de ingenierı́a neuromórfica cuya principal área de trabajo es el uso de VLSI analógicos, digitales, mixtos analógico/digital y software que implementa modelos de sistemas neuronales spiking. Esta tesis analiza las Redes Neuronales Spiking desde la perspectiva de Aprendizaje Automático, donde la plausibilidad biológica no es el objetivo principal, pero la capacidad de crear algoritmos de inteligencia artificial basados en SNN es uno de los objetivos principales, junto con su viabilidad de implementación de hardware. Con el fin de cumplir con los objetivos, varios modelos neuronales y topologı́as de red son revisados y comparados. La codificación de picos o la representación de datos con los picos también se discute en este trabajo. El desarrollo de topologı́as SNN y algoritmos capaces de proporcionar capacidades de inteligencia artificial basadas en espigas de entrada al sistema es uno de los principales temas de esta tesis. Sin embargo, se hace también hincapié en su implementación hardware ya que existen modelos complejos para SNN que en muchos casos no son viables para sistemas en tiempo real y requieren de sistemas de alta capacidad computacional para ser ejecutados. El tema principal de la investigación en este trabajo es la evaluación de algoritmos existentes y el desarrollo de nuevos algoritmos, estructuras de datos y métodos de codificación para la implementación hardware de las redes neuronales de spiking, especialmente dirigidas a FPGA (Field-Programmable Gate Arrays). Los dispositivos FPGA son elegidos debido a sus excelentes capacidades de cálculo paralelo masivo, bajo consumo de energı́a, baja latencia y versatilidad. En los últimos años, las FPGA se convirtieron en una popular plataforma para tareas clásicas de aprendizaje de máquinas, tales como reconocimiento de imágenes, control automático, predicción de series temporales, robótica, etc. Ası́, la tesis investiga todas las cuestiones relacionadas con el despliegue de un sistema completo de hardware basado en espigas, desde la codificación de información externa como entradas hasta la salida final de un sistema de inteligencia artificial basado en SNN, incluida la optimización en la transmisión de datos, y todo ello implementado en arquitecturas hardware que optimizan el rendimiento y permiten la implementación de redes spiking de un elevado número de neuronas. Se propone una nueva arquitectura simplificada de neuronas de tipo LIF (Leaky Integrate-and-Fire). La neurona se evalúa para redes de tipo Perceptron y Restricted Boltzmann Machine (RBM) para probar su rendimiento. Además, las capacidades de aprendizaje de las redes propuestas se desarrollan mediante la definición de un procedimiento optimizado para el aprendizaje de STDP (Spike Time Dependent Plasticity). Las propuestas de optimización en software son completadas por nuevas arquitecturas de hardware, especialmente diseñadas para la implementación de FPGA. En lo que se refiere a las arquitecturas de hardware, esta tesis define la llamada ”neurona autómata”, basada en un formato de representación de espigas novedoso también y definido en esta tesis, llamado ‘Variable Timeslot Length Address-Event Representation’ (VTSAER). Este formato tiene una mayor versatilidad que anteriores propuestas de AER, eliminando la necesidad de marcas de tiempo y permitiendo un verdadero sincronismo de cualquier número arbitrario de eventos. La estructura del VTSAER permite procesar la información en las neuronas de espigas como un autómata finito alimentado por eventos. Este nuevo enfoque ayuda a separar el estado del sistema de la tasa de entrada de datos y reducir el número de canales de entrada/salida. Otra novedad propuesta en esta tesis es una arquitectura vectorizada de capas de las redes neuronales. Esta arquitectura permite calcular el estado de cualquier número arbitrario de capas reutilizando los mismos bloques neuronales de hardware varias veces. Este concepto de procesamiento vectorial de datos se puede aplicar no sólo en las redes neuronales de espigas, sino también en redes neuronales clásicas no-spiking de tipo ANN y otros algoritmos de aprendizaje automático. Con la arquitectura vectorizada y la neurona autómata, el factor limitante para el tamaño de la red es sólo la cantidad de memoria en el FPGA, lo que es una mejora significativa a las implementaciones anteriores. En cuanto a los algoritmos de aprendizaje para SNN, esta tesis describe una nueva aplicación del algoritmo de aprendizaje de Spike Timing Dependent Plasticity. STDP sigue siendo el algoritmo de aprendizaje más popular para las redes neuronales spiking,derivado de las observaciones de los fenómenos biológicos. Implementaciones de hardware digital de la STDP rara vez se encuentran dado que el algoritmo está utilizando causalidad de sincronización hacia atrás que requiere un empleo significativo de recursos de hardware. La nueva implementación propuesta en esta tesis está resolviendo el problema de causalidad con una sobrecarga de hardware muy pequeña. La versión mejorada de STDP se puede utilizar en redes de número arbitrario de neuronas. El proceso de actualización de pesos es independiente para cada neurona y no afecta al flujo global de entrada de espigas. La implementación FPGA de algoritmos de codificación visual también se cubre en esta tesis. Se describe la codificación de campos receptivos visuales tipo Gabor y se presentan dos implementaciones de hardware. El método de codificación de campo receptivo es muy similar a la operación de convolución utilizada en redes neuronales no-spiking. Los campos especı́ficos de orientación de Gabor son importantes en el procesamiento de imágenes, ya que son fenómenos bien estudiados observados en la corteza visual de mamı́feros y se desempeñan bien en el procesamiento de imágenes y en las tareas de codificación de espigas. Las dos propuestas de implementación en FPGA son arquitectura paralela y vectorizada. La comparación se realiza utilizando tamaños de campo receptivo tı́picamente usados en tareas prácticas que muestran las posibilidades de aplicación para cada una de las propuestas de implementación. Además, la implementación del hardware digital de algoritmos requiere la adaptación de la aritmética, ya que la aritmética de punto fijo se utiliza para evitar la complejidad adicional dada por los cálculos de coma flotante. Por lo tanto, se realiza un extenso estudio de la aritmética de punto fijo en el hardware de codificación y procesamiento de spikes para probar que el punto fijo es capaz de proporcionar la exactitud y precisión requeridas a un menor costo computacional y de recursos. Todos los algoritmos y arquitecturas propuestos se prueban resolviendo problemas clásicos con bases de datos abiertos (open source) para poder hacer una comparación con otros autores: los conjuntos de datos SEMEION e Iris se utilizan en este caso. Con respecto a los resultados de hardware, las arquitecturas digitales propuestas permiten una alta frecuencia de operación de reloj, cercana al máximo permitido por el dispositivo FPGA (alcanza hasta 387MHz). Los algoritmos y arquitecturas propuestos también permiten SNN de tamaño arbitrario, limitándose sólo a la capacidad del dispositivo. Todas las cuestiones antes mencionadas forman una compleja solución novedosa para la implementación de redes neuronales de espigas en hardware FPGA con velocidad de procesamiento varios cientos de veces más rápido que las simulaciones de software y una precisión comparable. Los bloques de hardware propuestos son versátiles, capaces de implementar una amplia gama de modificaciones de los algoritmos descritos y adaptar múltiples topologı́as SNN con diferentes números de entradas, número de capas, número de neuronas por capa, número de salidas, longitud de bits y, en general, aquellos parámetros que permiten implementar múltiples formas de SNN. En total, utilizando los bloques de hardware desarrollados en esta tesis, es posible construir un sistema neuromórfico masivo autosuficiente con un ciclo de procesamiento completo hecho dentro de un chip. De este modo, los sistemas neuromórficos podrı́an ser implementados a un costo menor en términos de desarrollo y tiempo de diseño, junto con placas de hardware más simples.This thesis describes a novel architecture of the Spiking Neural Networks implemented in hardware using Field-Programmable Gate Arrays. By starting from the state of the art theoretical and practical works, a new approach to the problem is proposed. The presented work is dealing with both software and hardware topics such as: • Spiking neural models with focus on their performance and feasibility in hardware. A novel simplified neuron model is created and tested. • Learning of SNNs in software and hardware. The well-known learning algorithms are implemented and tested with the simplified neuron model. • Data representation and conversion in spiking neural systems. A new version of Address-Event Representation protocol is proposed, effectively allowing the finite automata approach to the SNN implementation. A novel hardware architecture to encode images is presented. • Hardware platforms’ resources and their usability for SNN implementation. The latest commercial FPGA devices are evaluated as the prospective platform for large-scale SNN implementation. • Spiking perceptron and spiking Restricted Boltzmann machine implementation. Two popular network models are implemented and tested, utilizing the proposed neuronal model. • Neural network learning in hardware. The previously studied algorithms are im- plemented in the hardware. The aforementioned material was partially published in two journal and five conference papers. The system has been fully developed and tested using public domain datasets

Advances in Bioengineering

The technological approach and the high level of innovation make bioengineering extremely dynamic and this forces researchers to continuous updating. It involves the publication of the results of the latest scientific research. This book covers a wide range of aspects and issues related to advances in bioengineering research with a particular focus on innovative technologies and applications. The book consists of 13 scientific contributions divided in four sections: Materials Science; Biosensors. Electronics and Telemetry; Light Therapy; Computing and Analysis Techniques

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc