Application of a Genetic Algorithm in a Fault-tolerant Filter

This paper presents an eighth order low-pass filter which has characteristics of fault tolerance through the use of evolvable hardware (EHW). A field programmable analog array (FPAA) is used to implement the filter under study. The reconfiguration process of the filter involves the execution of a genetic algorithm (GA) in an external computer, after a fault is detected. To perform the test of the filter, we assume that a frequency response characterization test is used. A parametric fault model that considers deviations in the values of one of the capacitors or one of the input amplifiers (IA) is used to evaluate the performance of developed GA. The results show that GA finds filter configurations that meet the restrictions set for all the simulated faults. Additionally, this work shows better results compared to those previously obtained using another EHW scheme for the same low-pass filter.Sociedad Argentina de Informática e Investigación Operativ

Application of a Genetic Algorithm in a Fault-tolerant Filter

This paper presents an eighth order low-pass filter which has characteristics of fault tolerance through the use of evolvable hardware (EHW). A field programmable analog array (FPAA) is used to implement the filter under study. The reconfiguration process of the filter involves the execution of a genetic algorithm (GA) in an external computer, after a fault is detected. To perform the test of the filter, we assume that a frequency response characterization test is used. A parametric fault model that considers deviations in the values of one of the capacitors or one of the input amplifiers (IA) is used to evaluate the performance of developed GA. The results show that GA finds filter configurations that meet the restrictions set for all the simulated faults. Additionally, this work shows better results compared to those previously obtained using another EHW scheme for the same low-pass filter.Sociedad Argentina de Informática e Investigación Operativ

Fault tolerance in an amplifier system implemented in reconfigurable system on chip platform

This work address the problem of providing fault tolerance to an analog system embedded in a commercial programmable system on chip. The system presents a functionality that has to be maintained despite the presence of faults, without direct human intervention. For detecting a gain fault, we use a built-in self-test strategy that establishes the actual values of gain achievable by the system. A simulated annealing (SA) algorithm finds the hardware configuration. The simulation results show that the strategy is able to maintain its functionality under the presence of catastrophic and deviation faults. In addition, SA presents better performance than an exhaustive search method.Centro de Técnicas Analógico-Digitale

Generalized disjunction decomposition for evolvable hardware

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the “generalized disjunction decomposition” (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the$(1 + lambda)$evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided

Definition, analysis and development of an optical data distribution network for integrated avionics and control systems

The potential and functional requirements of fiber optic bus designs for next generation aircraft are assessed. State-of-the-art component evaluations and projections were used in the system study. Complex networks were decomposed into dedicated structures, star buses, and serial buses for detailed analysis. Comparisons of dedicated links, star buses, and serial buses with and without full duplex operation and with considerations for terminal to terminal communication requirements were obtained. This baseline was then used to consider potential extensions of busing methods to include wavelength multiplexing and optical switches. Example buses were illustrated for various areas of the aircraft as potential starting points for more detail analysis as the platform becomes definitized

Application of a Genetic Algorithm in a Fault-tolerant Filter

This paper presents an eighth order low-pass filter which has characteristics of fault tolerance through the use of evolvable hardware (EHW). A field programmable analog array (FPAA) is used to implement the filter under study. The reconfiguration process of the filter involves the execution of a genetic algorithm (GA) in an external computer, after a fault is detected. To perform the test of the filter, we assume that a frequency response characterization test is used. A parametric fault model that considers deviations in the values of one of the capacitors or one of the input amplifiers (IA) is used to evaluate the performance of developed GA. The results show that GA finds filter configurations that meet the restrictions set for all the simulated faults. Additionally, this work shows better results compared to those previously obtained using another EHW scheme for the same low-pass filter.Sociedad Argentina de Informática e Investigación Operativ

System data communication structures for active-control transport aircraft, volume 2

The application of communication structures to advanced transport aircraft are addressed. First, a set of avionic functional requirements is established, and a baseline set of avionics equipment is defined that will meet the requirements. Three alternative configurations for this equipment are then identified that represent the evolution toward more dispersed systems. Candidate communication structures are proposed for each system configuration, and these are compared using trade off analyses; these analyses emphasize reliability but also address complexity. Multiplex buses are recognized as the likely near term choice with mesh networks being desirable for advanced, highly dispersed systems

Personalized Health Monitoring Using Evolvable Block-based Neural Networks

This dissertation presents personalized health monitoring using evolvable block-based neural networks. Personalized health monitoring plays an increasingly important role in modern society as the population enjoys longer life. Personalization in health monitoring considers physiological variations brought by temporal, personal or environmental differences, and demands solutions capable to reconfigure and adapt to specific requirements. Block-based neural networks (BbNNs) consist of 2-D arrays of modular basic blocks that can be easily implemented using reconfigurable digital hardware such as field programmable gate arrays (FPGAs) that allow on-line partial reorganization. The modular structure of BbNNs enables easy expansion in size by adding more blocks. A computationally efficient evolutionary algorithm is developed that simultaneously optimizes structure and weights of BbNNs. This evolutionary algorithm increases optimization speed by integrating a local search operator. An adaptive rate update scheme removing manual tuning of operator rates enhances the fitness trend compared to pre-determined fixed rates. A fitness scaling with generalized disruptive pressure reduces the possibility of premature convergence. The BbNN platform promises an evolvable solution that changes structures and parameters for personalized health monitoring. A BbNN evolved with the proposed evolutionary algorithm using the Hermite transform coefficients and a time interval between two neighboring R peaks of ECG signal, provides a patient-specific ECG heartbeat classification system. Experimental results using the MIT-BIH Arrhythmia database demonstrate a potential for significant performance enhancements over other major techniques

Autonomous Recovery Of Reconfigurable Logic Devices Using Priority Escalation Of Slack

Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases. To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Recon- figurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric. FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A iii significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria