32 research outputs found
Lightweight Strategy for XOR PUFs as Security Primitives for Resource-constrained IoT device
Physical Unclonable Functions (PUFs) are promising security primitives for
resource-constrained IoT devices. And the XOR Arbiter PUF (XOR-PUF) is one of
the most studied PUFs, out of an effort to improve the resistance against
machine learning attacks of probably the most lightweight delay-based PUFs -
the Arbiter PUFs. However, recent attack studies reveal that even XOR-PUFs with
large XOR sizes are still not safe against machine learning attacks. Increasing
PUF stages or components and using different challenges for different
components are two ways to improve the security of APUF-based PUFs, but more
stages or components lead to more hardware cost and higher operation power, and
different challenges for different components require the transmission of more
bits during operations, which also leads to higher power consumption. In this
paper, we present a strategy that combines the choice of XOR Arbiter PUF
(XOR-PUF) architecture parameters with the way XOR-PUFs are used to achieve
lightweights in hardware cost and energy consumption as well as security
against machine learning attacks. Experimental evaluations show that with the
proposed strategy, highly lightweight component-differentially challenged
XOR-PUFs can withstand the most powerful machine learning attacks developed so
far and maintain excellent intra-device and inter-device performance, rendering
this strategy a potential blueprint for the fabrication and use of XOR-PUFs for
resource-constrained IoT applications.Comment: arXiv admin note: text overlap with arXiv:2206.0131
Hybrid PUF Design using Bistable Ring PUF and Chaotic Network
Physical Unclonable Function(PUF) is lightweight hardware that provides affordable security for electronic devices and systems which can eliminate the use of the conventional cryptographic system which uses large area and storage. Among the several models, Bi-stable Ring PUF(BR-PUF) is considered as a secure and efficient PUF model since it has no mathematical model still found. In this thesis, we proposed a modified design called a hybrid model of BR-PUF and a Chaotic network to improve the BR-PUF resilience against machine learning attacks. We experimented with the current modification XOR technique to analyze the uniqueness, reliability and resource consumption. The proposed PUF was implemented on Xilinx Artix 7 FPGA and the PUF metrics were captured and compared with the results of XOR-ed based PUF integration techniques. The lightweight PUF model was achieved with 16% resource reduction when compared to XOR-ed BR PUF with no compromise in PUF quality
FPGA Based Arbiter Physical Unclonable Function Implementation with Reduced Hardware Overhead
The paper presents a new architecture of symmetric paths of the arbiter PUF, providing efficient use of the hardware resources of LUT blocks for various Xilinx Artix-7 FPGA family