Development of an FPGA-based gate signal generator for a multilevel inverter

The application of Field Programmable Gate Array (FPGA) in the development of power electronics circuits control scheme has drawn much attention lately due to its shorter design cycle, lower cost and higher density. This paper presents an FPGA-based gate signal generator for a multilevel inverter employing an online optimal PWM switching strategy to control its output voltage. FPGA is chosen for the hardware implementation of the switching strategy mainly due to its high computation speed that can ensure the accuracy of the instants that gating signals are generated. The gate signal generator has been realized by an FPGA (FLEXlOKZO) from Altera. The design and development of the FPGA based gate signal generator is described in detail. Results from the timing simulation using MAX+PLUSII software are given and verified by the results obtained from the FLEXlOK2O output

Development of an in-field tree imaging system : a thesis presented in partial fulfilment of the requirements for the degree of Master of Technology at Massey University

Quality inventory information is essential for optimal resource utilisation in the forestry industry. In-field tree imaging is a method which has been proposed to improve the preharvest inventor assessment of standing trees. It involves the application of digital imaging technology to this task. The method described generates a three dimensional model of each tree through the capture of two orthogonal images from ground level. The images are captured and analysed using the "TreeScan" in-field tree imaging system. This thesis describes the design, development, and evaluation of the TreeScan system. The thesis can also be used as a technical reference for the system and as such contains appropriate technical and design detail. The TreeScan system consists of a portable computer, a custom designed high resolution scanner with integral microcontroller, a calibration rod, and custom designed processing software. Images of trees are captured using the scanner which contains a CCD line scan camera and a precision scanning mechanism. Captured images are analysed on the portable computer using customised image processing software to estimate real world tree dimensions and shape. The TreeScan system provides quantitative estimates of five tree parameters; height, sweep, stem diameter, branch diameter, and feature separation such as internodal distance. In addition to these estimates a three dimensional model is generated which can be further processed to determine the optimal stem breakdown into logs

Data Cache-Energy and Throughput Models: Design Exploration for Embedded Processors

Most modern 16-bit and 32-bit embedded processors contain cache memories to further increase instruction throughput of the device. Embedded processors that contain cache memories open an opportunity for the low-power research community to model the impact of cache energy consumption and throughput gains. For optimal cache memory configuration mathematical models have been proposed in the past. Most of these models are complex enough to be adapted for modern applications like run-time cache reconfiguration. This paper improves and validates previously proposed energy and throughput models for a data cache, which could be used for overhead analysis for various cache types with relatively small amount of inputs. These models analyze the energy and throughput of a data cache on an application basis, thus providing the hardware and software designer with the feedback vital to tune the cache or application for a given energy budget. The models are suitable for use at design time in the cache optimization process for embedded processors considering time and energy overhead or could be employed at runtime for reconfigurable architectures

Portability, compatibility and reuse of MAC protocols across different IoT radio platforms

To cope with the diversity of Internet of Things (loT) requirements, a large number of Medium Access Control (MAC) protocols have been proposed in scientific literature, many of which are designed for specific application domains. However, for most of these MAC protocols, no multi-platform software implementation is available. In fact, the path from conceptual MAC protocol proposed in theoretical papers, towards an actual working implementation is rife with pitfalls. (i) A first problem is the timing bugs, frequently encountered in MAC implementations. (ii) Furthermore, once implemented, many MAC protocols are strongly optimized for specific hardware, thereby limiting the potential of software reuse or modifications. (iii) Finally, in real-life conditions, the performance of the MAC protocol varies strongly depending on the actual underlying radio chip. As a result, the same MAC protocol implementation acts differently per platform, resulting in unpredictable/asymmetrical behavior when multiple platforms are combined in the same network. This paper describes in detail the challenges related to multi-platform MAC development, and experimentally quantifies how the above issues impact the MAC protocol performance when running MAC protocols on multiple radio chips. Finally, an overall methodology is proposed to avoid the previously mentioned cross-platform compatibility issues. (C) 2018 Elsevier B.V. All rights reserved

Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed

RIOT OS Paves the Way for Implementation of High-Performance MAC Protocols

Implementing new, high-performance MAC protocols requires real-time features, to be able to synchronize correctly between different unrelated devices. Such features are highly desirable for operating wireless sensor networks (WSN) that are designed to be part of the Internet of Things (IoT). Unfortunately, the operating systems commonly used in this domain cannot provide such features. On the other hand, "bare-metal" development sacrifices portability, as well as the mul-titasking abilities needed to develop the rich applications that are useful in the domain of the Internet of Things. We describe in this paper how we helped solving these issues by contributing to the development of a port of RIOT OS on the MSP430 microcontroller, an architecture widely used in IoT-enabled motes. RIOT OS offers rich and advanced real-time features, especially the simultaneous use of as many hardware timers as the underlying platform (microcontroller) can offer. We then demonstrate the effectiveness of these features by presenting a new implementation, on RIOT OS, of S-CoSenS, an efficient MAC protocol that uses very low processing power and energy.Comment: SCITEPRESS. SENSORNETS 2015, Feb 2015, Angers, France. http://www.scitepress.or

Racing to hardware-validated simulation

Processor simulators rely on detailed timing models of the processor pipeline to evaluate performance. The diversity in real-world processor designs mandates building flexible simulators that expose parts of the underlying model to the user in the form of configurable parameters. Consequently, the accuracy of modeling a real processor relies on both the accuracy of the pipeline model itself, and the accuracy of adjusting the configuration parameters according to the modeled processor. Unfortunately, processor vendors publicly disclose only a subset of their design decisions, raising the probability of introducing specification inaccuracies when modeling these processors. Inaccurately tuning model parameters deviates the simulated processor from the actual one. In the worst case, using improper parameters may lead to imbalanced pipeline models compromising the simulation output. Therefore, simulation models should be hardware-validated before using them for performance evaluation. As processors increase in complexity and diversity, validating a simulator model against real hardware becomes increasingly more challenging and time-consuming. In this work, we propose a methodology for validating simulation models against real hardware. We create a framework that relies on micro-benchmarks to collect performance statistics on real hardware, and machine learning-based algorithms to fine-tune the unknown parameters based on the accumulated statistics. We overhaul the Sniper simulator to support the ARM AArch64 instruction-set architecture (ISA), and introduce two new timing models for ARM-based in-order and out-of-order cores. Using our proposed simulator validation framework, we tune the in-order and out-of-order models to match the performance of a real-world implementation of the Cortex-A53 and Cortex-A72 cores with an average error of 7% and 15%, respectively, across a set of SPEC CPU2017 benchmarks