A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure

2D Detectors for Particle Physics and for Imaging Applications

The demands on detectors for particle detection as well as for medical and astronomical X-ray imaging are continuously pushing the development of novel pixel detectors. The state of the art in pixel detector technology to date are hybrid pixel detectors in which sensor and read-out integrated circuits are processed on different substrates and connected via high density interconnect structures. While these detectors are technologically mastered such that large scale particle detectors can be and are being built, the demands for improved performance for the next generation particle detectors ask for the development of monolithic or semi-monolithic approaches. Given the fact that the demands for medical imaging are different in some key aspects, developments for these applications, which started as particle physics spin-off, are becomming rather independent. New approaches are leading to novel signal processing concepts and interconnect technologies to satisfy the need for very high dynamic range and large area detectors. The present state in hybrid and (semi-)monolithic pixel detector development and their different approaches for particle physics and imaging application is reviewed

Algorithm-circuit co-design for detecting symptomatic patterns in biological signals

The advancement in scaled Silicon technology has accelerated the development of a wide range of applications in various fields including medical technology. It has immensely contributed to finding solutions for monitoring general health as well as alleviating intractable disorders in the form of implantable and wearable systems. This necessitates the development of energy efficient and functionally efficacious systems. This thesis has explored the algorithm-circuit co-design approach for developing an energy efficient epileptic seizure detection processor which could be used for implantable epilepsy prosthesis. Novel wavelet transform based algorithms are proposed for accurate detection of epileptic seizures. Energy efficient techniques at circuit level such as power and clock gating are utilized along with error resiliency at algorithm level to implement these algorithms in TSMC $65$nm bulk-Si technology. Furthermore, the methodology is extended to develop a generic pattern detection system, which could be used for health monitoring. The wavelet transform along with mathematical metrics and Mel cepstrum are used to develop an algorithm which can detect generic patterns in biological audio signals. The application of algorithm-circuit co-design methodology helps in practically implementing this system into a low power design. Using approximation of coefficients and multiplier-less implementation, the Mel cepstrum algorithm is modified to optimize the hardware cost without losing its functional efficacy. The system is user-specific and scalable for detecting various patterns in biological signals. The methodologies mentioned in this thesis are intended towards development of user-scalable, energy efficient and highly efficacious systems for detection of patterns in variety of biological signals

Structure and realization of pole-shared switched-current complex wavelet filter

A pole-shared switched-current complex wavelet filter structure with follow-the-leader feedback configuration is proposed for synthesizing the real and imaginary approximation functions with the same poles. The double-sampling fully-balanced SI bilinear integrator and current mirror are employed as the building cells. By sharing the implementation circuit for approximation poles of the real and the imaginary part, the proposed structure only has the same circuit complexity as that of real-valued wavelet filter, which is very suitable for small-size and low-power application. The complex Morlet wavelet is selected as an example to elaborate the design procedure. Simulation results confirm that the presented complex wavelet filter structure can generate the real and imaginary coefficients of complex wavelet transform accurately with simple synthesis method and explicit design formulas.Peer reviewedFinal Accepted Versio

A new power MEMS component with variable capacitance

Autonomous devices such as wireless sensors and sensor networks need a long battery lifetime in a small volume. Incorporating micro-power generators based on ambient energy increases the lifetime of these systems while reducing the volume. This paper describes a new approach to the conversion of mechanical energy, available in vibrations, to electrical energy. The conversion principle is based on charge transportation between two parallel capacitors. An electret is used to polarize the device. A large-signal model was developed, allowing simulations of the behavior of the generator. A small-signal model was then derived in order to quantify the output power as a function of the design parameters. These models show the possibility of generating up to 40 muW with a device of 10 mm 2. A layout was made based on a standard SOI-technology, available in an MPW. With this design a power of 1 muW at 1020 Hz is expected

A 0.6V 2.9µW mixed-signal front-end for ECG monitoring

This paper presents a mixed-signal ECG front-end that uses aggressive voltage scaling to maximize power-efficiency and facilitate integration with low-voltage DSPs. 50/60Hz interference is canceled using mixed-signal feedback, enabling ultra-low-voltage operation by reducing dynamic range requirements. Analog circuits are optimized for ultra-low-voltage, and a SAR ADC with a dual-DAC architecture eliminates the need for a power-hungry ADC buffer. Oversampling and ΔΣ-modulation leveraging near-V[subscript T] digital processing are used to achieve ultra-low-power operation without sacrificing noise performance and dynamic range. The fully-integrated front-end is implemented in a 0.18μm CMOS process and consumes 2.9μW from 0.6V.Texas Instruments IncorporatedNatural Sciences and Engineering Research Council of Canada (Fellowship