Bus interconnection networks

AbstractIn bus interconnection networks every bus provides a communication medium between a set of processors. These networks are modeled by hypergraphs where vertices represent the processors and edges represent the buses. We survey the results obtained on the construction methods that connect a large number of processors in a bus network with given maximum processor degree Δ, maximum bus size r, and network diameter D. (In hypergraph terminology this problem is known as the (Δ,D, r)-hypergraph problem.)The problem for point-to-point networks (the case r = 2) has been extensively studied in the literature. As a result, several families of networks have been proposed. Some of these point-to-point networks can be used in the construction of bus networks. One approach is to consider the dual of the network. We survey some families of bus networks obtained in this manner. Another approach is to view the point-to-point networks as a special case of the bus networks and to generalize the known constructions to bus networks. We provide a summary of the tools developed in the theory of hypergraphs and directed hypergraphs to handle this approach

Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures

This work proposes a general framework for the design and simulation of network on chip based turbo decoder architectures. Several parameters in the design space are investigated, namely the network topology, the parallelism degree, the rate at which messages are sent by processing nodes over the network and the routing strategy. The main results of this analysis are: i) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de-Bruijn and generalized Kautz topologies; ii) depending on the throughput requirements different parallelism degrees, message injection rates and routing algorithms can be used to minimize the network area overhead.Comment: submitted to IEEE Trans. on Circuits and Systems I (submission date 27 may 2009

Counting Euler Tours in Undirected Bounded Treewidth Graphs

We show that counting Euler tours in undirected bounded tree-width graphs is tractable even in parallel - by proving a $\#SAC^1$ upper bound. This is in stark contrast to #P-completeness of the same problem in general graphs. Our main technical contribution is to show how (an instance of) dynamic programming on bounded \emph{clique-width} graphs can be performed efficiently in parallel. Thus we show that the sequential result of Espelage, Gurski and Wanke for efficiently computing Hamiltonian paths in bounded clique-width graphs can be adapted in the parallel setting to count the number of Hamiltonian paths which in turn is a tool for counting the number of Euler tours in bounded tree-width graphs. Our technique also yields parallel algorithms for counting longest paths and bipartite perfect matchings in bounded-clique width graphs. While establishing that counting Euler tours in bounded tree-width graphs can be computed by non-uniform monotone arithmetic circuits of polynomial degree (which characterize $\#SAC^1$) is relatively easy, establishing a uniform $\#SAC^1$ bound needs a careful use of polynomial interpolation.Comment: 17 pages; There was an error in the proof of the GapL upper bound claimed in the previous version which has been subsequently remove

Connectivity of consecutive-d digraphs

AbstractThe concept of consecutive-d digraph is proposed by Du, Hsu and Hwang. It generalizes the class of de Bruijin digraphs, the class of Imase-Itoh digraphs and the class of generalized de Bruijin graphs. We modify consecutive-d digraphs by connecting nodes with a loop into a circuit and deleting all loops. The result in this paper shows that the link-connectivity or the connectivity of modified consecutive-d digraphs get better