106 research outputs found

    Implementing a Self-Checking Profibus Slave

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    This work presents the study and preliminary results of the high level implementation of a self-checking Profibus slave. From an existing VHDL description of the device, a test strategy was studied and implemented, so that the whole circuit has embedded test structures capable to perform at-speed test of the slave. In this paper, we show the used test strategies and implementation results achieved from a synthesis process in a FPGA environment

    Phase Locking Authentication for Scan Architecture

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    Scan design is a widely used Design for Testability (DfT) approach for digital circuits. It provides a high level of controllability and observability resulting in a high fault coverage. To achieve a high level of testability, scan architecture must provide access to the internal nodes of the circuit-under-test (CUT). This access however leads to vulnerability in the security of the CUT. If an unrestricted access is provided through a scan architecture, unlimited test vectors can be applied to the CUT and its responses can be captured. Such an unrestricted access to the CUT can potentially undermine the security of the critical information stored in the CUT. There is a need to secure scan architecture to prevent hardware attacks however a secure solution may limit the CUT testability. There is a trade-off between security and testability, therefore, a secure scan architecture without hindering its controllability and observability is required. Three solutions to secure scan architecture have been proposed in this thesis. In the first method, the tester is authenticated and the number of authentication attempts has been limited. In the second method, a Phase Locked Loop (PLL) is utilized to secure scan architecture. In the third method, the scan architecture is secured through a clock and data recovery (CDR) technique. This is a manuscript based thesis and the results of this study have been published in two conference proceedings. The latest results have also been prepared as an article for submission to a high rank conference

    High level behavioural modelling of boundary scan architecture.

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    This project involves the development of a software tool which enables the integration of the IEEE 1149.1/JTAG Boundary Scan Test Architecture automatically into an ASIC (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 1076 Hardware Description Language. The tool consists of the two major elements: i) A parsing and insertion algorithm developed and implemented in 'C'; ii) A high level model of the Boundary Scan Test Architecture implemented in 'VHDL'. The parsing and insertion algorithm is developed to deal with identifying the design Input/Output (I/O) terminals, their types and the order they appear in the ASIC design. It then attaches suitable Boundary Scan Cells to each I/O, except power and ground and inserts the high level models of the full Boundary Scan Architecture into the ASIC without altering the design core structure

    A Hardware Security Solution against Scan-Based Attacks

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    Scan based Design for Test (DfT) schemes have been widely used to achieve high fault coverage for integrated circuits. The scan technique provides full access to the internal nodes of the device-under-test to control them or observe their response to input test vectors. While such comprehensive access is highly desirable for testing, it is not acceptable for secure chips as it is subject to exploitation by various attacks. In this work, new methods are presented to protect the security of critical information against scan-based attacks. In the proposed methods, access to the circuit containing secret information via the scan chain has been severely limited in order to reduce the risk of a security breach. To ensure the testability of the circuit, a built-in self-test which utilizes an LFSR as the test pattern generator (TPG) is proposed. The proposed schemes can be used as a countermeasure against side channel attacks with a low area overhead as compared to the existing solutions in literature

    Cost modelling and concurrent engineering for testable design

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    This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.As integrated circuits and printed circuit boards increase in complexity, testing becomes a major cost factor of the design and production of the complex devices. Testability has to be considered during the design of complex electronic systems, and automatic test systems have to be used in order to facilitate the test. This fact is now widely accepted in industry. Both design for testability and the usage of automatic test systems aim at reducing the cost of production testing or, sometimes, making it possible at all. Many design for testability methods and test systems are available which can be configured into a production test strategy, in order to achieve high quality of the final product. The designer has to select from the various options for creating a test strategy, by maximising the quality and minimising the total cost for the electronic system. This thesis presents a methodology for test strategy generation which is based on consideration of the economics during the life cycle of the electronic system. This methodology is a concurrent engineering approach which takes into account all effects of a test strategy on the electronic system during its life cycle by evaluating its related cost. This objective methodology is used in an original test strategy planning advisory system, which allows for test strategy planning for VLSI circuits as well as for digital electronic systems. The cost models which are used for evaluating the economics of test strategies are described in detail and the test strategy planning system is presented. A methodology for making decisions which are based on estimated costing data is presented. Results of using the cost models and the test strategy planning system for evaluating the economics of test strategies for selected industrial designs are presented

    Metacognitive awareness : impact of a metacognitive intervention in a pre-nursing course

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    To function effectively as nurses in the evolving, complex healthcare system, nursing students must learn to be skilled thinkers, know how to learn, and know how to use what they know in novel situations. Research in the field of metacognition may offer a useful framework to improve learning and to enhance critical thinking and clinical decision-making in nursing students. The purpose of this study is to describe how pre-nursing students’ self-reported metacognitive awareness correlates with age and academic variables and to explore the effects of a metacognitive intervention on students’ metacognitive awareness. Using a quasi-experimental research design, the study consisted of a pre-test, an intervention, and a post-test with no control group. Students in a pre-nursing course completed the Metacognitive Awareness Inventory (MAI) before and after a metacognitive intervention. Students’ pre-test scores on the MAI were correlated to age and academic indicators including overall College grade point average (GPA), nursing GPA, and standardized test scores on the Test of Essential Academic Skills (TEAS). Post-test MAI scores were correlated with grades on the final reflective portfolio, a course-specific academic indicator. The study also analyzed whether or not there was a statistically significant increase in MAI scores following a metacognitive intervention. Results of the study indicated that, in adult pre-nursing students, metacognitive awareness is not correlated with age or academic indicators. Following the metacognitive intervention, there was a statistically significant increase in students’ knowledge of cognition. Increases in total MAI scores and regulation of cognition scores were not statistically significant. Recommendations for improvements in faculty development related to metacognition and metacognitive interventions and implications for future research are discussed

    Alaska native corporations: participation, purpose, and performance in for-profit indigenous businesses

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    Alaska Native Corporations (ANCs) were established under the Alaska Native Claims Settlement Act in 1971 to extinguish Indigenous land claims in the state of Alaska, as well as to provide for the economic and social wellbeing of Alaska Natives. However, ANCs’ governance practices and performance record offer a mixed record of their ability to incorporate the voice of their Indigenous shareholders and to fulfill a broad mandate for economic and social wellbeing among Alaska Natives. This exploratory, sequential, mixed methods study examines the relationship between shareholder participation, purpose, and performance in ANCs. Synthesizing theories from multiple domains, this study clarifies what is meant by inclusive governance. Additionally, it offers a new understanding of individual-level and firm-level benefits of shareholder participation, as well as an emergent model of the antecedents of inclusive governance, centered on shareholder participation. It advances an understanding of the motivations for stakeholder participation embedded in the context of Indigenous organizations. For a practitioner audience, this study offers advice to enable a more inclusive, participatory governance process in Indigenous and non-Indigenous businesses alike. It describes how a participatory process may help to allay the concerns of some shareholder groups and may maximize both the objective and perceived benefits of corporate social responsibility practices

    Computer-Based Diagnostic Systems: Computer-Based Troubleshooting

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    Spartan Daily, October 6, 1998

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    Volume 111, Issue 26https://scholarworks.sjsu.edu/spartandaily/9314/thumbnail.jp
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