Design-for-test structure to facilitate test vector application with low performance loss in non-test mode.

A switching based circuit is described which allows application of voltage test vectors to internal nodes of a chip without the problem of backdriving. The new circuit has low impact on the performance of an analogue circuit in terms of loss of bandwidth and allows simple application of analogue test voltages into internal nodes. The circuit described facilitates implementation of the forthcoming IEEE 1149.4 DfT philosophy [1]

Analog integrated neural-like circuits for nonlinear programming

A systematic approach for the design of analog neural nonlinear programming solvers using switched-capacitor (SC) integrated circuit techniques is presented. The method is based on formulating a dynamic gradient system whose state evolves in time towards the solution point of the corresponding programming problem. A neuron cell for the linear and the quadratic problem suitable for monolithic implementation is introduced. The design of this neuron and its corresponding synapses using SC techniques is considered in detail. An SC circuit architecture based on a reduced set of basic building blocks with high modularity is presented. Simulation results using a mixed-mode simulator (DIANA) and experimental results from breadboard prototypes are included, illustrating the validity of the proposed technique

Improving circuit miniaturization and its efficiency using Rough Set Theory

High-speed, accuracy, meticulousness and quick response are notion of the vital necessities for modern digital world. An efficient electronic circuit unswervingly affects the maneuver of the whole system. Different tools are required to unravel different types of engineering tribulations. Improving the efficiency, accuracy and low power consumption in an electronic circuit is always been a bottle neck problem. So the need of circuit miniaturization is always there. It saves a lot of time and power that is wasted in switching of gates, the wiring-crises is reduced, cross-sectional area of chip is reduced, the number of transistors that can implemented in chip is multiplied many folds. Therefore to trounce with this problem we have proposed an Artificial intelligence (AI) based approach that make use of Rough Set Theory for its implementation. Theory of rough set has been proposed by Z Pawlak in the year 1982. Rough set theory is a new mathematical tool which deals with uncertainty and vagueness. Decisions can be generated using rough set theory by reducing the unwanted and superfluous data. We have condensed the number of gates without upsetting the productivity of the given circuit. This paper proposes an approach with the help of rough set theory which basically lessens the number of gates in the circuit, based on decision rules.Comment: The International Conference on Machine Intelligence Research and Advancement,ICMIRA-201

Biometric multimodal security simulation on schedule Ii controlled drug

The paper present a multimodal (multi biometrics) security system focusing on the implementation of fingerprint recognition and facial feature recognition to enhance the existing method of security using password or personal identification number (PIN). This project is operated through a personal computer where all the identification for fingerprint and facial feature are done by using specific software. Successful identification will send a signal through a serial communication circuit and open an application. In this project, the final application should be a cupboard that store and secure schedule II controlled drug in hospital. Due to some problem, the final application was replaced by using a light emitting diode (LED) simulation circuit

Implementing Non-Projective Measurements via Linear Optics: an Approach Based on Optimal Quantum State Discrimination

We discuss the problem of implementing generalized measurements (POVMs) with linear optics, either based upon a static linear array or including conditional dynamics. In our approach, a given POVM shall be identified as a solution to an optimization problem for a chosen cost function. We formulate a general principle: the implementation is only possible if a linear-optics circuit exists for which the quantum mechanical optimum (minimum) is still attainable after dephasing the corresponding quantum states. The general principle enables us, for instance, to derive a set of necessary conditions for the linear-optics implementation of the POVM that realizes the quantum mechanically optimal unambiguous discrimination of two pure nonorthogonal states. This extends our previous results on projection measurements and the exact discrimination of orthogonal states.Comment: final published versio

Concrete resource analysis of the quantum linear system algorithm used to compute the electromagnetic scattering cross section of a 2D target

We provide a detailed estimate for the logical resource requirements of the quantum linear system algorithm (QLSA) [Phys. Rev. Lett. 103, 150502 (2009)] including the recently described elaborations [Phys. Rev. Lett. 110, 250504 (2013)]. Our resource estimates are based on the standard quantum-circuit model of quantum computation; they comprise circuit width, circuit depth, the number of qubits and ancilla qubits employed, and the overall number of elementary quantum gate operations as well as more specific gate counts for each elementary fault-tolerant gate from the standard set {X, Y, Z, H, S, T, CNOT}. To perform these estimates, we used an approach that combines manual analysis with automated estimates generated via the Quipper quantum programming language and compiler. Our estimates pertain to the example problem size N=332,020,680 beyond which, according to a crude big-O complexity comparison, QLSA is expected to run faster than the best known classical linear-system solving algorithm. For this problem size, a desired calculation accuracy 0.01 requires an approximate circuit width 340 and circuit depth of order $10^{25}$ if oracle costs are excluded, and a circuit width and depth of order $10^8$ and $10^{29}$, respectively, if oracle costs are included, indicating that the commonly ignored oracle resources are considerable. In addition to providing detailed logical resource estimates, it is also the purpose of this paper to demonstrate explicitly how these impressively large numbers arise with an actual circuit implementation of a quantum algorithm. While our estimates may prove to be conservative as more efficient advanced quantum-computation techniques are developed, they nevertheless provide a valid baseline for research targeting a reduction of the resource requirements, implying that a reduction by many orders of magnitude is necessary for the algorithm to become practical.Comment: 37 pages, 40 figure