Reusing RTL assertion checkers for verification of SystemC TLM models

The recent trend towards system-level design gives rise to new challenges for reusing existing RTL intellectual properties (IPs) and their verification environment in TLM. While techniques and tools to abstract RTL IPs into TLM models have begun to appear, the problem of reusing, at TLM, a verification environment originally developed for an RTL IP is still under-explored, particularly when ABV is adopted. Some frameworks have been proposed to deal with ABV at TLM, but they assume a top-down design and verification flow, where assertions are defined ex-novo at TLM level. In contrast, the reuse of existing assertions in an RTL-to-TLM bottom-up design flow has not been analyzed yet, except by using transactors to create a mixed simulation between the TLM design and the RTL checkers corresponding to the assertions. However, the use of transactors may lead to longer verification time due to the need of developing and verifying the transactors themselves. Moreover, the simulation time is negatively affected by the presence of transactors, which slow down the simulation at the speed of the slowest parts (i.e., RTL checkers). This article proposes an alternative methodology that does not require transactors for reusing assertions, originally defined for a given RTL IP, in order to verify the corresponding TLM model. Experimental results have been conducted on benchmarks with different characteristics and complexity to show the applicability and the efficacy of the proposed methodology

Cross-Layer Rapid Prototyping and Synthesis of Application-Specific and Reconfigurable Many-accelerator Platforms

Technological advances of recent years laid the foundation consolidation of informatisationof society, impacting on economic, political, cultural and socialdimensions. At the peak of this realization, today, more and more everydaydevices are connected to the web, giving the term ”Internet of Things”. The futureholds the full connection and interaction of IT and communications systemsto the natural world, delimiting the transition to natural cyber systems and offeringmeta-services in the physical world, such as personalized medical care, autonomoustransportation, smart energy cities etc. . Outlining the necessities of this dynamicallyevolving market, computer engineers are required to implement computingplatforms that incorporate both increased systemic complexity and also cover awide range of meta-characteristics, such as the cost and design time, reliabilityand reuse, which are prescribed by a conflicting set of functional, technical andconstruction constraints. This thesis aims to address these design challenges bydeveloping methodologies and hardware/software co-design tools that enable therapid implementation and efficient synthesis of architectural solutions, which specifyoperating meta-features required by the modern market. Specifically, this thesispresents a) methodologies to accelerate the design flow for both reconfigurableand application-specific architectures, b) coarse-grain heterogeneous architecturaltemplates for processing and communication acceleration and c) efficient multiobjectivesynthesis techniques both at high abstraction level of programming andphysical silicon level.Regarding to the acceleration of the design flow, the proposed methodologyemploys virtual platforms in order to hide architectural details and drastically reducesimulation time. An extension of this framework introduces the systemicco-simulation using reconfigurable acceleration platforms as co-emulation intermediateplatforms. Thus, the development cycle of a hardware/software productis accelerated by moving from a vertical serial flow to a circular interactive loop.Moreover the simulation capabilities are enriched with efficient detection and correctiontechniques of design errors, as well as control methods of performancemetrics of the system according to the desired specifications, during all phasesof the system development. In orthogonal correlation with the aforementionedmethodological framework, a new architectural template is proposed, aiming atbridging the gap between design complexity and technological productivity usingspecialized hardware accelerators in heterogeneous systems-on-chip and networkon-chip platforms. It is presented a novel co-design methodology for the hardwareaccelerators and their respective programming software, including the tasks allocationto the available resources of the system/network. The introduced frameworkprovides implementation techniques for the accelerators, using either conventionalprogramming flows with hardware description language or abstract programmingmodel flows, using techniques from high-level synthesis. In any case, it is providedthe option of systemic measures optimization, such as the processing speed,the throughput, the reliability, the power consumption and the design silicon area.Finally, on addressing the increased complexity in design tools of reconfigurablesystems, there are proposed novel multi-objective optimization evolutionary algo-rithms which exploit the modern multicore processors and the coarse-grain natureof multithreaded programming environments (e.g. OpenMP) in order to reduce theplacement time, while by simultaneously grouping the applications based on theirintrinsic characteristics, the effectively explore the design space effectively.The efficiency of the proposed architectural templates, design tools and methodologyflows is evaluated in relation to the existing edge solutions with applicationsfrom typical computing domains, such as digital signal processing, multimedia andarithmetic complexity, as well as from systemic heterogeneous environments, suchas a computer vision system for autonomous robotic space navigation and manyacceleratorsystems for HPC and workstations/datacenters. The results strengthenthe belief of the author, that this thesis provides competitive expertise to addresscomplex modern - and projected future - design challenges.Οι τεχνολογικές εξελίξεις των τελευταίων ετών έθεσαν τα θεμέλια εδραίωσης της πληροφοριοποίησης της κοινωνίας, επιδρώντας σε οικονομικές,πολιτικές, πολιτιστικές και κοινωνικές διαστάσεις. Στο απόγειο αυτής τη ςπραγμάτωσης, σήμερα, ολοένα και περισσότερες καθημερινές συσκευές συνδέονται στο παγκόσμιο ιστό, αποδίδοντας τον όρο «Ίντερνετ των πραγμάτων».Το μέλλον επιφυλάσσει την πλήρη σύνδεση και αλληλεπίδραση των συστημάτων πληροφορικής και επικοινωνιών με τον φυσικό κόσμο, οριοθετώντας τη μετάβαση στα συστήματα φυσικού κυβερνοχώρου και προσφέροντας μεταυπηρεσίες στον φυσικό κόσμο όπως προσωποποιημένη ιατρική περίθαλψη, αυτόνομες μετακινήσεις, έξυπνες ενεργειακά πόλεις κ.α. . Σκιαγραφώντας τις ανάγκες αυτής της δυναμικά εξελισσόμενης αγοράς, οι μηχανικοί υπολογιστών καλούνται να υλοποιήσουν υπολογιστικές πλατφόρμες που αφενός ενσωματώνουν αυξημένη συστημική πολυπλοκότητα και αφετέρου καλύπτουν ένα ευρύ φάσμα μεταχαρακτηριστικών, όπως λ.χ. το κόστος σχεδιασμού, ο χρόνος σχεδιασμού, η αξιοπιστία και η επαναχρησιμοποίηση, τα οποία προδιαγράφονται από ένα αντικρουόμενο σύνολο λειτουργικών, τεχνολογικών και κατασκευαστικών περιορισμών. Η παρούσα διατριβή στοχεύει στην αντιμετώπιση των παραπάνω σχεδιαστικών προκλήσεων, μέσω της ανάπτυξης μεθοδολογιών και εργαλείων συνσχεδίασης υλικού/λογισμικού που επιτρέπουν την ταχεία υλοποίηση καθώς και την αποδοτική σύνθεση αρχιτεκτονικών λύσεων, οι οποίες προδιαγράφουν τα μετα-χαρακτηριστικά λειτουργίας που απαιτεί η σύγχρονη αγορά. Συγκεκριμένα, στα πλαίσια αυτής της διατριβής, παρουσιάζονται α) μεθοδολογίες επιτάχυνσης της ροής σχεδιασμού τόσο για επαναδιαμορφούμενες όσο και για εξειδικευμένες αρχιτεκτονικές, β) ετερογενή αδρομερή αρχιτεκτονικά πρότυπα επιτάχυνσης επεξεργασίας και επικοινωνίας και γ) αποδοτικές τεχνικές πολυκριτηριακής σύνθεσης τόσο σε υψηλό αφαιρετικό επίπεδο προγραμματισμού,όσο και σε φυσικό επίπεδο πυριτίου.Αναφορικά προς την επιτάχυνση της ροής σχεδιασμού, προτείνεται μια μεθοδολογία που χρησιμοποιεί εικονικές πλατφόρμες, οι οποίες αφαιρώντας τις αρχιτεκτονικές λεπτομέρειες καταφέρνουν να μειώσουν σημαντικά το χρόνο εξομοίωσης. Παράλληλα, εισηγείται η συστημική συν-εξομοίωση με τη χρήση επαναδιαμορφούμενων πλατφορμών, ως μέσων επιτάχυνσης. Με αυτόν τον τρόπο, ο κύκλος ανάπτυξης ενός προϊόντος υλικού, μετατεθειμένος από την κάθετη σειριακή ροή σε έναν κυκλικό αλληλεπιδραστικό βρόγχο, καθίσταται ταχύτερος, ενώ οι δυνατότητες προσομοίωσης εμπλουτίζονται με αποδοτικότερες μεθόδους εντοπισμού και διόρθωσης σχεδιαστικών σφαλμάτων, καθώς και μεθόδους ελέγχου των μετρικών απόδοσης του συστήματος σε σχέση με τις επιθυμητές προδιαγραφές, σε όλες τις φάσεις ανάπτυξης του συστήματος. Σε ορθογώνια συνάφεια με το προαναφερθέν μεθοδολογικό πλαίσιο, προτείνονται νέα αρχιτεκτονικά πρότυπα που στοχεύουν στη γεφύρωση του χάσματος μεταξύ της σχεδιαστικής πολυπλοκότητας και της τεχνολογικής παραγωγικότητας, με τη χρήση συστημάτων εξειδικευμένων επιταχυντών υλικού σε ετερογενή συστήματα-σε-ψηφίδα καθώς και δίκτυα-σε-ψηφίδα. Παρουσιάζεται κατάλληλη μεθοδολογία συν-σχεδίασης των επιταχυντών υλικού και του λογισμικού προκειμένου να αποφασισθεί η κατανομή των εργασιών στους διαθέσιμους πόρους του συστήματος/δικτύου. Το μεθοδολογικό πλαίσιο προβλέπει την υλοποίηση των επιταχυντών είτε με συμβατικές μεθόδους προγραμματισμού σε γλώσσα περιγραφής υλικού είτε με αφαιρετικό προγραμματιστικό μοντέλο με τη χρήση τεχνικών υψηλού επιπέδου σύνθεσης. Σε κάθε περίπτωση, δίδεται η δυνατότητα στο σχεδιαστή για βελτιστοποίηση συστημικών μετρικών, όπως η ταχύτητα επεξεργασίας, η ρυθμαπόδοση, η αξιοπιστία, η κατανάλωση ενέργειας και η επιφάνεια πυριτίου του σχεδιασμού. Τέλος, προκειμένου να αντιμετωπισθεί η αυξημένη πολυπλοκότητα στα σχεδιαστικά εργαλεία επαναδιαμορφούμενων συστημάτων, προτείνονται νέοι εξελικτικοί αλγόριθμοι πολυκριτηριακής βελτιστοποίησης, οι οποίοι εκμεταλλευόμενοι τους σύγχρονους πολυπύρηνους επεξεργαστές και την αδρομερή φύση των πολυνηματικών περιβαλλόντων προγραμματισμού (π.χ. OpenMP), μειώνουν το χρόνο επίλυσης του προβλήματος της τοποθέτησης των λογικών πόρων σε φυσικούς,ενώ ταυτόχρονα, ομαδοποιώντας τις εφαρμογές βάση των εγγενών χαρακτηριστικών τους, διερευνούν αποτελεσματικότερα το χώρο σχεδίασης.Η αποδοτικότητά των προτεινόμενων αρχιτεκτονικών προτύπων και μεθοδολογιών επαληθεύτηκε σε σχέση με τις υφιστάμενες λύσεις αιχμής τόσο σε αυτοτελής εφαρμογές, όπως η ψηφιακή επεξεργασία σήματος, τα πολυμέσα και τα προβλήματα αριθμητικής πολυπλοκότητας, καθώς και σε συστημικά ετερογενή περιβάλλοντα, όπως ένα σύστημα όρασης υπολογιστών για αυτόνομα διαστημικά ρομποτικά οχήματα και ένα σύστημα πολλαπλών επιταχυντών υλικού για σταθμούς εργασίας και κέντρα δεδομένων, στοχεύοντας εφαρμογές υψηλής υπολογιστικής απόδοσης (HPC). Τα αποτελέσματα ενισχύουν την πεποίθηση του γράφοντα, ότι η παρούσα διατριβή παρέχει ανταγωνιστική τεχνογνωσία για την αντιμετώπιση των πολύπλοκων σύγχρονων και προβλεπόμενα μελλοντικών σχεδιαστικών προκλήσεων

A Middleware-centric design methodology for networked embedded systems

Negli ultimi anni \ue8 incrementato considerevolmente l\u2019interesse verso gli \u201dambient intelligence\u201d, sistemi informatici, tipicamente composti da \u201dnetworked embedded systems\u201d (Wirelesse sensor networks, mobile terminal, PDA, etc.) i quali sono integrati nell\u2019ambiente umano con l\u2019obiettivo di migliorare la qualit`a della vita nel modo pi naturale possibile. Una applicazione \u201dNetworked Embedded System\u201d (NES) \ue8 un\u2019applicazione distribuita, eseguita su piattaforme HW/SW eterogenee che interagiscono attraverso differenti canali di comunicazione. Generalmente queste applicazioni per dispositivi NES vengono sviluppate senza il supporto di software di sistema, obbligando il progettista a modellare queste applicazioni utilizzando direttamente le primitive fornite dal sistema operativo embedded o le API dei drivers dei dispositivi HW. Con questa metodologia di progettazione, le applicazioni per sistemi embedded vengono realizzate ad-hoc per la piattaforma HW/SW, risultando essere n\ue9 portabili, n\ue9 scalabili e di conseguenza particolarmente costose. A causa di questi problemi, negli ultimi anni si \ue8 adottato un flusso di progettazione che prevede l\u2019introduzione di un \u201dservice layer\u201d chiamato middleware, il quale astrae le peculiarit del sistema operativo e dei componenti HW, semplificando la progettazione di queste applicazioni embedded. Allo stato dell\u2019arte sono presenti molte implmentazioni di middleware con differenti paradigmi di programmazione, e la scelta di quale utilizzare per progettazione una applicazione NES basata sui seguenti criteri: \u2022 abilit`a/conoscenza/capacit`a di programmazione da parte del progettista; \u2022 piattaforma HW/SW disponinile. Gli svantaggi di questo approccio sono un pi\uf9 complesso flusso di progettazione legato alla mancanza di portabilit\ue0 della stessa applicazione su differenti dispositivi embedded. Questo significa che la presenza del middleware non \ue8 mai stata introdotta nel flusso di progettazione come una esplicita dimensione di progetto. Obiettivo della tesi di dottorato \ue8 lo studio e la realizzazione di un flusso di progettazione per applicazioni per NES, dove il middleware \ue8 una dimensione di progetto, diventando una variabile di progetto come lo sono il software e lo hardware. Questo punto \ue8 ottenuto risolvendo tre problemi: \u2022 Fornire un modello di middleware astratto il quale pu\uf2 essere usato come componente del flusso di progettazione; questo middleware astratto, chiamato Abstract Middleware Services (AMS), fornisce un insieme di servizi astratti basati su differenti paradigmi di programmazione dei middleware reali. Utilizzando questo modello di middleware stratto, il progettista \ue8 facilitato nello sviluppo delle applicazioni per NES. \u2022 Fornire un ambiente di simulazione dove validare e simulare l\u2019intero modello realizzato dal progettista. \u2022 Fornire una metodologia automatica di traduzione da AMS ad un middleware reale, per poter eseguire l\u2019applicazione su una reale piattaforma HW/SW, dotata di un middleware qualsiasi. L\u2019attivit di dototrato ha permesso la definizione di un nuovo approccio di progettazione basato su un modello di middleware astratto che fornisce un ambiente per la modellazione e la validazione di applicazioni per Networked Embedded Systems, risolvendo i tre punti precedenti. Inoltre, al fine di produrre un efficiente ambiente di simulazione e modellazione, sono state analizzate le metodologie di co-simulazione hardware-software-network attualmente presenti in letteratura. L\u2019attivit\ue0 di dottorato inoltre parte integrante del progetto ANGEL finanziato dalla Comunit\ue0 Europea (IST-2005-33506 - Embedded Systems), il cui obiettivo \ue8 lo sviluppo di una piattaforma per la realizzazione di sistemi eterogenei nei quali Wireless Sensor Network (WSN) e tradizionali reti di comunicazioni cooperano per monitorare e migliorare la qualit\ue0 della vita in habitat comuni. Durante questa attivit\ue0 il flusso di progettazione che include anche il middleware come variabile di progetto, oggetto della tesi di dottorato, sar esemplificato su WSN e terminali mobili (per esempio cellulari) per far si che questi possano dialogare tra loro in modo intelligente.Ambient intelligence, pervasive and ubiquitous computing are the center of a great deal of attention because of their promise to bring benefits for end-users, higher revenues for manufacturers and new challenges for researchers. Typical computing technologies (such as telemedicine, manufacturing, crisis management) are part of a broader class of Networked Embedded Systems (NES) in which a large number of nodes are connected together and collaborate to perform a common task under a defined set of constraints. Therefore, the key aspects of these applications are their distributed nature and the presence of very limited HW resources, as in case of WSNs. Their wide adoption requires interoperability across different manufacturers, simplification of application development, simulation tools for functional validation and the fulfilment of tight HW/SW constraints. Interoperability is achieved through the use of standard protocol stacks (e.g., IEEE 802.15.1/Bluetooth and IEEE 802.15.4/Zig- Bee). Simplification of application development can be achieved through a service layer, named middleware, which abstracts from the peculiarities of the operating system and HW components. Traditionally, many NES applications have been developed without support from system software [1] excepts for device drivers and operating systems. State-of-the-art techniques [2] for NES focus on simple data-gathering applications, and in most cases, the design of the application and the system software are usually closely-coupled, or even combined as a monolithic procedure. Such applications are neither flexible nor scalable and they should be re-written if the platform changes. Middleware is emerging as an important architectural component in supporting NES applications able to facilitate the application development. The role of middleware is to present a unified programmingmodel to application designers and to mask out the problems of heterogeneity and distribution providing a basic set of tools and libraries for the low-level handling of technology-specific NES. Several NES middleware have been implemented in the past years each one providing different programming paradigms (e.g., Tuplespace, messageoriented, object-oriented, database, etc.) and differ with respect to ease to use, expressiveness, scalability and overhead. However, their diversity makes the development of high quality middleware-centric software systems complex: software engineering methods and tools should be developed with the use of middleware in mind. In such way, Sensation [xxx] presents a middleware platform solution for pervasive applications inWSN providing a developer-friendly programming interface. This approach is valid just for WSN and does not include a network simulator for an exhaustive network evaluation. Model Driven Architecture (MDA) tries to overcome this problem; MDA is a new way of writing specifications, based on a platform-independent model. A complete MDA specification consists of a platform-independent UML model, one or more platform-specific models, and interface definitions, each describing how the base model is implemented on a different middleware platform. The MDA focuses primarily on the functionality and behaviour of a distributed application or system, not on the technology in which it will be implemented. Furthermore,MDA does not directly provide a simulation environment. Simulation tools are used for validating the application: there is a range of NES simulators available that focus on the network itself. NS-2 is a pure network simulator tool, where the nodes are abstracted and do not run real codes or operating systems, but rather simple behavioral models or statistical traffic generators. The advantage of NS-2 is that scalability is excellent. TOSSIM is a platform-specific simulator environment for sensor networks based on TinyOs operating system. TOSSIM can compile unchanged TinyOS applications directly into its framework, which means that most of the codes written for TOSSIM can be directly used in TinyOS. TOSSIM is a specific simulator for TinyOS and Berkeley motes and cant be used for simulating a generic NES (e.g.,WSN). Finally, SIMICS is a commercial full-system simulator that can be used to simulate heterogenous networked and distributed systems. Complete SW stacks from real system can run on the simulator without any modification. Despite of these punctual contributions, the literature does not report a complete design methodology for NES applications integrating all such three aspects. Therefore, in order to fully support the applications of a great variety of users with different needs, a complete NES application modelling and simulation environment have to include two main components: \u2022 a simulator to validate and explore application functional behaviuor in a network simulated environment supporting interoperability between different implementation platforms and ensure scalability of the NES technology. \u2022 a middleware environemnt providing different programming paradigms. This Layer will serve as an abstraction layer hiding the different NES implementations peculiarities from end-user applications. The goal of this work is to present a middleware-centric design flow for NES, where the middleware plays a decisive role in the design process. The proposed methodology allows programmers to write NES applications by using the system description language named SystemC and the AbstractMiddleware Environment (AME) framework for fast simulation. This proposal has three main advantages: (1) It provides a set of abstract services supporting the programming paradigms of different actual middleware implementations in order to meet the skills of the designer. AME facilitates the NES design flow by providing a unified and developer-common interface concealing the peculiarities of the underlying NES where the simulation environment is modelled in order to simulate the NES applications taking in account hardware and network effects. (2) The application can be simulated at early stage of the design flow for functional validation. (3) automatic mapping of AME applications on the actual platform; this guarantees the correct trade-off between level of abstraction and efficiency of implementation. In the follow we classify the actual middleware approaches according to their programming paradigms; then the AMEcentric design flow is described and finally we report the experimental results

High-level synthesis for FPGAs: From prototyping to deployment

Abstract-Escalating System-on-Chip design complexity is pushing the design community to raise the level of abstraction beyond RTL. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS methodology is happening now, especially for FPGA designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. Index Terms-Domain-specific design, field-programmable gate array (FPGA), high-level synthesis (HLS), quality of results (QoR)

Guarded atomic actions and refinement in a system-on-chip development flow: bridging the specification gap with Event-B

Modern System-on-chip (SoC) hardware design puts considerable pressure on existing design and verification flows, languages and tools. The Register Transfer Level (RTL)description, which forms the input for synchronous, logic synthesis-driven design is at too low a level of abstraction for efficient architectural exploration and re-use. The existing methods for taking a high-level paper specification and refining this specification to an implementation that meets its performance criteria is largely manual and error-prone and as RTL descriptions get larger, a systematic design method is necessary to address explicitly the timing issues that arise when applying logic synthesis to such large blocks.Guarded Atomic Actions have been shown to offer a convenient notation for describing microarchitectures that is amenable to formal reasoning and high-level synthesis. Event-B is a language and method that supports the development of specifications with automatic proof and refinement, based on guarded atomic actions. Latency-insensitive design ensures that a design composed of functionally correct components will be independent of communication latency. A method has been developed which uses Event-B for latency-insensitive SoC component and sub-system design which can be combined with high-level, component synthesis to enable architectural exploration and re-use at the specification level and to close the specification gap in the SoC hardware flow

Dynamic Assertion-Based Verification for SystemC

SystemC has emerged as a de facto standard modeling language for hardware and embedded systems. However, the current standard does not provide support for temporal specifications. Specifically, SystemC lacks a mechanism for sampling the state of the model at different types of temporal resolutions, for observing the internal state of modules, and for integrating monitors efficiently into the model's execution. This work presents a novel framework for specifying and efficiently monitoring temporal assertions of SystemC models that removes these restrictions. This work introduces new specification language primitives that (1) expose the inner state of the SystemC kernel in a principled way, (2) allow for very fine control over the temporal resolution, and (3) allow sampling at arbitrary locations in the user code. An efficient modular monitoring framework presented here allows the integration of monitors into the execution of the model, while at the same time incurring low overhead and allowing for easy adoption. Instrumentation of the user code is automated using Aspect-Oriented Programming techniques, thereby allowing the integration of user-code-level sample points into the monitoring framework. While most related approaches optimize the size of the monitors, this work focuses on minimizing the runtime overhead of the monitors. Different encoding configurations are identified and evaluated empirically using monitors synthesized from a large benchmark of random and pattern temporal specifications. The framework and approaches described in this dissertation allow the adoption of assertion-based verification for SystemC models written using various levels of abstraction, from system level to register-transfer level. An advantage of this work is that many existing specification languages call be adopted to use the specification primitives described here, and the framework can easily be integrated into existing implementations of SystemC

Optimierung der Energie und Power getriebenen Architekturexploration für Multicore und heterogenes System on Chip

The contribution of this work builds on top of the established virtual prototype platforms to improve both SoC design quality and productivity. Initially, an automatic system-level power estimation framework was developed to address the critical issue of early power estimation in SoC design. The estimation framework models the static and dynamic power consumption of the hardware components. These models are created from the normalized values of the basic design components of SoC, obtained through one-time power simulation of RTL hardware models. The framework allows dynamic technology node reconfiguration for power estimation models. Its instantaneous power reporting aids the detection of possible hotspot early into the design process. Adding this additional data in conjunction with a steadily growing design space of complex heterogeneous SoC, finding the right parameter configuration is a challenging and laborious task for a system-level designer. This work addresses this bottleneck by optimizing the design space exploration (DSE) process for MPSoC design. An automatic DSE framework for virtual platforms (VPs) was developed which is flexible and allows the selection optimal parameter configuration without pre-existing knowledge. To reduce exploration time, the framework is equipped with several multi-objective optimization techniques based on simulated annealing and a genetic algorithm. Lastly, to aid HW/SW partitioning at system-level, a flexible and automated workflow (SW2TLM) is presented. It allows the designer to explore various possible partitioning scenarios without going into depth of the hardware architecture complexity and software integration. The framework generates system-level hardware accelerators from corresponding functionality encoded in the software code and integrates them into the VP. Power consumption and time speedups of acceleration is reported to the designer, which further increases the quality and productivity of the development process towards the final architecture. The presented tools are evaluated using a state-of-the-art VP for a range of single and multi-core applications. Viewing the energy delay product, a reduction in exploration time was recorded at approximately 62% (worst case), maintaining optimal parameter accuracy of 90% compared to previous techniques. While the SW2TLM further increases the exploration versatility by combining modern high-level synthesis with system-level architectural exploration.Der Beitrag dieser Arbeit baut auf dem etablierten Konzept der virtuellen Prototyp (VP) Plattformen auf, um die Qualität und die Produktivität des Entwurfsprozesses zu verbessern. Zunächst wurde ein automatisches System-Level-Framework entwickelt, um Verlustleistungsabschätzung für SoC-Designs in einer deutlich früheren Entwicklungsphase zu ermöglichen. Hierfür werden statischen und dynamischen Energieverbrauchsanteile individueller Hardwareelemente durch ein abstraktes Modell ausgedrückt. Das Framework ermöglicht eine dynamische Anpassung des Technologieknotens sowie die Integration neuer Leistungsmodelle für Drittanbieterkomponenten. Die kontinuierliche Erfassung der Energieverbrauchseigenschaften und ihre grafische Darstellung Benutzeroberfläche unterstützt zusätzlich die frühzeitige Identifikation möglicher Hotspots. Durch die Bereitstellung zusätzlicher Daten, in Verbindung mit einem stetig wachsenden Entwurfsraum komplexer SoCs, ist die Identifikation der richtigen Parameterkonfiguration eine zeitintensive Aufgabe. Die vorgelegten Konzepte erlauben eine gesteigerte Automatisierung des Explorationsprozesses. Techniken der mehrdimensionalen Optimierung, basierend auf Simulated Annealing und genetischer Algorithmen erlauben die Identifikation von geeigneten Konfigurationen ohne vorheriges Wissen oder Erfahrungswerte Schließlich wurde zur Unterstützung der HW/SW -Partitionierung auf System-Ebene ein flexibler und automatisierter Workflow entwickelt. Er ermöglicht es dem Designer verschiedene mögliche Partitionierungsszenarien zu untersuchen, ohne sich in die Komplexität der Hardwarearchitektur und der Softwareintegration zu vertiefen. Das Framework erzeugt abstrakte Beschleunigermodelle aus entsprechenden Softwarefunktionen und integriert sie nahtlos in den ausführbare VP. Detaillierte Daten zum Energieverbrauch, Beschleunigungsfaktor und Kommunikationsoverhead der Partitionierung werden erfasst und dem Designer zur Verfügung gestellt, was die Qualität und Produktivität des weiter erhöht. Die vorgestellten Tools werden mit einer modernen VP für verschiedene SW-Anwendungen evaluiert. Bei Betrachtung des Energieverzögerungsprodukts wurde eine Verringerung der Explorationszeit um mehr als 62% bei 90% Parametergenauigkeit festgestell. Darauf aufbauend, erleichtert die automatisierte Untersuchung verschiedener HW/SW Partitionierungen die Entwicklung heterogener Architekturen durch die Kombination moderner HLS mit Architektur-Exploration auf der Systemebene

Verificação funcional pós-particionamento em sistemas integrados de hardware e software

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Ciência da Computação.O escopo tradicional da veri¯ca»c~ao funcional foi ampliado com o surgimento dos °uxos de projeto em n¶³vel de sistema eletr^onico (ESL). Nesses °u-xos, logo ap¶os o particionamento hardware-software, a veri¯ca»c~ao precisa lidar com tipos abstratos de dados, com artefatos de implementa»c~ao e com a poss¶³vel n~ao-preserva»c~ao, no dispositivo sob veri¯ca»c~ao (DUV), da ordem dos comportamentos no modelo de refer^encia (golden model ). As t¶ecnicas existentes para veri¯ca»c~ao p¶os-particionamento est~ao limitadas pelo uso de heur¶³sticas (que colocam em risco as garantias de veri¯ca»c~ao) ou por abordagens black-box (que restringem a observabilidade). Este trabalho adota uma abordagem white-box e prop~oe uma nova t¶ecnica que opera sobre amostras de dados capturadas por monitores e armazenadas na forma dos assim-chamados logs. Para cada ponto a ser veri¯cado, inserem-se monitores espelhados: um no modelo de refer^encia, outro no DUV. A veri¯ca»c~ao autom¶atica dos logs ¶e formulada com um problema de casamento (matching) em um grafo bipartido. O problema cl¶assico foi modi¯cado para capturar n~ao apenas a compatibilidade de valores monitorados, mas tamb¶em a preced^encia de eventos, de forma a viabilizar o tratamento da n~ao-preserva»c~ao da ordem no DUV. A formula»c~ao adotada permitiu provar v¶arias propriedades, as quais foram utilizadas como base te¶orica para determinar as garantias de veri¯ca»c~ao da t¶ecnica proposta. A implementa»c~ao dos monitores utilizou infra-estrutura pr¶e-existente baseada em re°ex~ao computacional. S~ao apresentados resultados experimentais que validam a formula»c~ao e os algoritmos propostos. The traditional scope of functional veri¯cation has been extended with the rise of electronic-system-level (ESL) design °ows. In those °ows, immediately after hardware-software partitioning, veri¯cation has to deal with abstract data, with implementation artifacts, and, possibly, with the non-preservation, by the device under veri¯cation (DUV), of the the order of behaviors at the golden model. Existing approaches are limited either by the use of greedy heuristics (jeopardizing veri¯cation guarantees) or by black-box approaches (impairing observability). This work adopts a white-box approach and proposes a new technique that operates on data samples captured by monitors and stored in the form of so-called logs. For each point to be veri¯ed, mirrored monitors are inserted: one at the golden model, another at the DUV. The automatic veri¯cation of the logs of a pair of mirrored monitors is cast as a bipartite graph matching problem. The classical problem was modi¯ed to capture not only value compatibility, but also event precedence, so as to allow the treatment of the non-preserved event order at the DUV. The adopted formulation allowed us to prove several properties, which were used as stepping stones for determining the veri¯cation guarantees of the proposed technique. The implementation of monitors relied on pre-existing infrastructure based upon computational re°ection. Experimental results validate the formulation and the proposed algorithms