Voltage drop tolerance by adaptive voltage scaling using clock-data compensation

Proyecto de Graduación (Maestría en Ingeniería en Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2019.El ruido de alta frecuencia en la red de alimentación compromete el rendimiento y la eficiencia energética de los sistemas electrónicos con microprocesadores, restringiendo la frecuencia máxima de operación de los sistemas y disminuyendo la confiabilidad de los dispositivos. La frecuencia máxima será determinada por la ruta de datos más crítica (la ruta de datos más lenta). De esta manera, es necesario configurar una banda de guarda para tolerar caídas de voltaje sin tener ningún problema de ejecución, pero sacrificando el rendimiento eléctrico. Este trabajo evalúa el impacto de la caída de voltaje en el rendimiento de los circuitos CMOS de alta densidad, estableciendo un conjunto de casos de prueba que contienen diferentes configuraciones de circuitos. Se desarrolló una técnica adaptable y escalable para mejorar la tolerancia a la caída de voltaje en los circuitos CMOS a través del escalado adaptativo, aprovechando el efecto de compensación de datos del reloj. La solución propuesta se validó aplicándola a diferentes casos de prueba en una tecnología FinFet-CMOS a nivel de simulación del diseño físico.High-frequency power supply noise compromises performance and energy efficiency of microprocessor-based products, restricting the maximum frequency of operation for electronic systems and decreasing device reliability. The maximum frequency is going to be determine by the most critical data path (the slowest data path). In this way, a guard band needs to be set in order to tolerate voltage drops without having any execution problem, but leading to a performance reduction. This work evaluates the impact of voltage drop in the performance of CMOS circuits by establishing a set of test cases containing different circuit configurations. An adaptive and scalable technique is proposed to enhance voltage drop tolerance in CMOS circuits through adaptive scaling, taking advantage of the clock-data compensation effect. The proposed solution is validated by applying it to different test cases in a FinFet CMOS technology at a post-layout simulation level

Millimeter and sub-millimeter wave radiometers for atmospheric remote sensing from CubeSat platforms

2018 Fall.Includes bibliographical references.To view the abstract, please see the full text of the document

On-detector electronics for high speed data transport, control and power distribution for the LHCb VELO and ATLAS Pixel Upgrades

The Large Hadron Collider (LHC) will see an upgrade to higher luminosity to widen the scope of study of particle physics and this will be a major upgrade of the LHC. The LHC collides protons at an energy of 13 TeV in order to study the fundamental components of matter and the forces that bind them together. The High-Luminosity Large Hadron Collider (HL-LHC) will enter service after 2025, increasing the volume of the data for analysis by a factor of 10. The phenomena that physicists are looking for have a very low probability of occurring and this is why a very large amount of data is needed to detect them. Vertexing and tracking sub-detectors for these High Energy Physics (HEP) experiments deliver very high data rates that require multi-gigabit transmission links. Commercial solutions such as optical transmission or wire cabling are investigated, however, due to high radiation environments and low radiation length requirements, electrical transmission with low mass custom designs have to be considered. Designing transmission lines with this requirement does pose a challenge and optical data transmission is used when space and radiation limits allow. The increase in luminosity will produce more data making it possible to study the phenomena in more detail by increasing the number of collisions by a factor of between five and seven. The increase in data will require an enhanced readout system and related electronics to be able to transmit and read out the data for further processing. At the same time powering systems need to be looked at to understand cost effcient and reliable techniques to be able to power such electronics. The thesis focuses on the readout electronics of the LHCb Vertex Locator (known as the 'VELO') Upgrade and the ATLAS Inner Tracker (known as the 'ITk') Upgrade including design of some components of the sub-systems, testing for high-speed data signaling, powering schemes and analysis of PCB designs and scope for improvements. An introduction to the LHC and the four experiments that use its beam - ATLAS, CMS, ALICE and LHCb is outlined. The thesis work is focused on two of these detectors namely ATLAS (A Toroidal LHC ApparatuS) and LHCb (Large Hadron Collider beauty) and these are further explained and details of the sub-systems that make up these detectors are elaborated. Major differences to the upgrade of the experiments is explained highlighting the changes and the main challenges that would need to be addressed. The work on the On-detector electronics of the LHCb VELO Upgrade with details of the design requirements and implementations for the different components is described and test results are presented. Data tapes for carrying high speed data signals and control signals from the front-end chip to the Vacuum Feedthoough (VF) were designed and successfully tested to have a loss of < 10 dB at the Nyquist frequency of 2.5 GHz and a characteristic impedance of approximately 94 Ω which is within the 10% tolerance of 100 Ω for differential signals. Sensitivity to radiation damage as well as additional mass in the detector acceptance were some factors that motivated the design of the Opto Power board (OPB). In addition, there was a need to power the front-end ASICs but from outside the vacuum tank. The OPB was designed to meet these requirements in addition to be more easily accessible for repair and maintenance. The OPB is realised in an 8-layer stackup, with custom designed radiation hard ICs, and was designed for optical to electrical conversion of 20 high-speed data links at 5.12 Gb/s per link to be read by the Off-detector electronics. The board comprises 13 DC-DC converters for powering 12 ASICs, two front-end hybrids and the OPB itself with a total current supply of 26 A. The ATLAS experiment will implement the Inner Tracker (ITk) which is a new tracker to be installed during the major ATLAS Upgrade during Long Shutdown 3. The work on the ATLAS ITK addresses two topics; a novel pixel powering scheme adopting layout techniques for high-speed design. A serial powering scheme was evaluated to be an optimal option and this scheme was tested to understand its scope and implementation in the pixel endcap design and results are presented. A study to understand the existing Crescent Tape PCB layout and techniques to improve the design for high-speed data transmission was evaluated. Methods for analysing high-speed data using S-parameters and eye diagrams, sources of signal degradation and mitigation techniques, are detailed. The laboratory test setup for high-speed measurements with the equipments used is also explained

Ingress of threshold voltage-triggered hardware trojan in the modern FPGA fabric–detection methodology and mitigation

The ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship’s integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillator-based sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation

On-Chip Power Supply Noise: Scaling, Suppression and Detection

Design metrics such as area, timing and power are generally considered as the primary criteria in the design of modern day circuits, however, the minimization of power supply noise, among other noise sources, is appreciably more important since not only can it cause a degradation in these parameters but can cause entire chips to fail. Ensuring the integrity of the power supply voltage in the power distribution network of a chip is therefore crucial to both building reliable circuits as well as preventing circuit performance degradation. Power supply noise concerns, predicted over two decades ago, continue to draw significant attention, and with present CMOS technology projected to keep on scaling, it is shown in this work that these issues are not expected to diminish. This research also considers the management and on-chip detection of power supply noise. There are various methods of managing power supply noise, with the use of decoupling capacitors being the most common technique for suppressing the noise. An in-depth analysis of decap structures including scaling effects is presented in this work with corroborating silicon results. The applicability of various decaps for given design constraints is provided. It is shown that MOS-metal hybrid structures can provide a significant increase in capacitance per unit area compared to traditional structures and will continue to be an important structure as technology continues to scale. Noise suppression by means of current shifting within the clock period of an ALU block is further shown to be an additional method of reducing the minimum voltage observed on its associated supply. A simple, and area and power efficient technique for on-chip supply noise detection is also proposed

Subsynchronous resonance risk assessment in interconnected power systems

 Series compensation and high voltage direct current (HVDC) links, technically increase the viability of suppling remote areas by long loading transmission lines, or connecting new remote generation hub to the main network. Nowadays such technologies have become part of utilities’ plans to increase power transfer capability between regions. This is usually due to lack of local reserve within a region under system wide contingencies or when there is redundancy of large unscheduled generation (usually in case of extensive wind generation during low demand durations). Both series compensation and HVDC converters excite frequencies below the synchronous frequency of the system called subsynchronous frequencies. These frequencies will be seen as voltage and current components superimposed on the 50 Hz voltage and current signals. These components may excite tortional torque at the adjacent generator causing excessive voltages and currents, and damage to the generator–turbine shaft. Subsynchronous currents or voltages can also be generated in power systems as inter-harmonics emission from a distorting load such as HV high-capacity variable speed drives (VSDs). In other cases, a series resonance between the cables’ capacitance and the transformer’s inductance can occur, resulting in resonant frequency components. Under all these circumstances, there is a risk of SSR conditions. Subsynchronous resonance will become an important network condition to investigate when the new technologies are introduced in power systems. The purpose of this research is to establish understanding of challenges and issues facing the power networks planning, in particular the SSR conditions. The thesis presents key characteristics of power systems and modelling considerations, which need to be taken into account for SSR assessment. Further, a good understanding of the general requirements and criteria for addressing SSR problems is established. Design requirements for HVDC links and series compensation to reduce the risk of SSR are presented. A guide for power system elements representation for simulation studies is established. New modelling and simulation approaches for SSR analysis are proposed to overcome the difficulty of incorporating the discrete nature of the operation of Thyristor Controlled Series Capacitor (TCSC). A computation algorithm for eigenvalue calculation is developed based on Time Frequency Distribution (TFD) concept, by capturing the time variation of a frequency component. The disproportion between the cost of mitigation solution and the cost implication of the risk of low probability condition such as SSR conditions led the utilities to underestimate the risk, thus increasing the system vulnerability to failure. Two context are realised in SSR risk, firstly is the system states probability and the correlation with SSR risk, and secondly the relationship between SSR risk and the system’s operating conditions. The probability weighted cost implication of the SSR risk is estimated and compared with the cost of mitigation measure. This comparison will assist in the economical justification of the countermeasure. It is concluded that it is possible to optimise system’s operating condition to achieve acceptable risk of SSR by quantifying a relationship between system’s constraints and the system’s operating conditions

Compendium of Computational Tools for Power Systems Harmonic Analysis

Harmonic analysis comes into limelight at this contemporary world as a result of proliferation of non-linear loads producing waveform distortions in power systems. It has apparently outshined other important phrases such as power outage, power factor and so on which are known for their devastating impacts. The emergence of distorted waveform has adverse effects which could be slow or rapid damage of key apparatus and equipment, namely power transformers, electric motors and other sensitive computer as well as communication facilities. In fact, it is very easy to assess the menace of power outage or power factor since both the utility and consumers keep watchdog on their billings/operating costs in case of power factor or the economic losses when there is outage. Unfortunately, the detection of harmonics could only be analysed using high-tech power systems harmonic analysers and there is a need to provide stakeholders in the industry compendium of computational tools for fast harmonic analysis. Thus, the harmonic data acquired were used to train an artificial neural network (ANN) implemented on MATrix LABoratory (MATLAB 8) software platform to facilitate accurate prediction of harmonic distortions

Fault Diagnosis and Condition Monitoring of Power Electronic Components Using Spread Spectrum Time Domain Reflectometry (SSTDR) and the Concept of Dynamic Safe Operating Area (SOA)

Title from PDF of title page viewed April 1, 2021Dissertation advisors: Faisal Khan and Yong ZengVitaIncludes bibliographical references ( page 117-132)Thesis (Ph.D.)--School of Computing and Engineering and Department of Mathematics and Statistics. University of Missouri--Kansas City, 2021Fault diagnosis and condition monitoring (CM) of power electronic components with a goal of improving system reliability and availability have been one of the major focus areas in the power electronics field in the last decades. Power semiconductor devices such as metal oxide semiconductor field-effect transistor (MOSFET) and insulated-gate bipolar transistor (IGBT) are considered to be the most fragile element of the power electronic systems and their reliability degrades with time due to mechanical and thermo-electrical stresses, which ultimately leads to a complete failure of the overall power conversion systems. Therefore, it is important to know the present state of health (SOH) of the power devices and the remaining useful life (RUL) of a power converter in order to perform preventive scheduled maintenance, which will eventually lead to increased system availability and reduced cost. In conventional practice, device aging and lifetime prediction techniques rely on the estimation of the meantime to failure (MTTF), a value that represents the expected lifespan of a device. MTTF predicts expected lifespan, but cannot adequately predict failures attributed to unusual circumstances or continuous overstress and premature degradation. This inability is due in large part to the fact that it considers the device safe operating area (SOA) or voltage and current ride-through capability to be independent of SOH. However, we experimentally proved that SOA of any semiconductor device goes down with the increased level of aging, and therefore, the probability of occurrence of over-voltage/current situation increases. As a result, the MTTF of the device as well as the overall converter reliability reduces with aging. That said, device degradation can be estimated by accomplishing an accurate online degradation monitoring tool that will determine the dynamic SOA. The correlation between aging and dynamic SOA gives us the useful remaining life of the device or the availability of a circuit. For this monitoring tool, spread spectrum time domain reflectometry (SSTDR) has been proposed and was successfully implemented in live power converters. In SSTDR, a high-frequency sine-modulated pseudo-noise sequence (SMPNS) is sent through the system, and reflections from age-related impedance discontinuities return to the test end where they are analyzed. In the past, SSTDR has been successfully used for device degradation detection in power converters while running at static conditions. However, the rapid variation in impedance throughout the entire live converter circuit caused by the fast-switching operation makes CM more challenging while using SSTDR. The algorithms and techniques developed in this project have overcome this challenge and demonstrated that the SSTDR test data are consistent with the aging of the power devices and do not affect the switching performance of the modulation process even the test signal is applied across the gate-source interface of the power MOSFET. This implies that the SSTDR technique can be integrated with the gate driver module, thereby creating a new platform for an intelligent gate-driver architecture (IGDA) that enables real-time health monitoring of power devices while performing features offered by a commercially available driver. Another application of SSTDR in power electronic systems is the ground fault prediction and detection technique for PV arrays. Protecting PV arrays from ground faults that lead to fire hazards and power loss is imperative to maintaining safe and effective solar power operations. Unlike many standard detection methods, SSTDR does not depend on fault current, therefore, can be implemented for testing ground faults at night or low illumination. However, wide variation in impedance throughout different materials and interconnections makes fault location more challenging than fault detection. This barrier was surmounted by the SSTDR-based fault detection algorithm developed in this project. The proposed algorithm was accounted for any variation in the number of strings, fault resistance, and the number of faults. In addition to its general utility for fault detection, the proposed algorithm can identify the location of multiple faults using only a single measurement point, thereby working as a preventative measure to protect the entire system at a reduced cost. Within the scope of the research work on SSTDR-based fault diagnosis and CM of power electronic components, a cell-level SOH measurement tool has been proposed that utilizes SSTDR to detect the location and aging of individual degraded cells in a large series-parallel connected Li-ion battery pack. This information of cell level SOH along with the respective cell location is critical to calculating the SOH of a battery pack and its remaining useful lifetime since the initial SOH of Li-ion cells varies under different manufacturing processes and operating conditions, causing them to perform inconsistently and thereby affect the performance of the entire battery pack in real-life applications. Unfortunately, today’s BMS considers the SOH of the entire battery pack/cell string as a single SOH and therefore, cannot monitor the SOH at the cell level. A healthy battery string has a specific impedance between the two terminals, and any aged cell in that string will change the impedance value. Since SSTDR can characterize the impedance change in its propagation path along with its location, it can successfully locate the degraded cell in a large battery pack and thereby, can prevent premature failure and catastrophic danger by performing scheduled maintenance.Introduction -- Background study and literature review -- Fundamentals of Spread Spectrum Time Domain Reflectometry (SSTDR): A new method for testing electronics live -- Accelerated aging test bench: design and implementation -- Condition monitoring of power switching in live power switching devices in live power electronic converters using SSTDR -- An irradiance-independent, robust ground-fault detection scheme for PV arrays based on SSTDR -- Detection of degraded/aged cell in a LI-Ion battery pack using SSTDR -- Dynamiv safe operating area (SOA) of power semiconductor devices -- Conclusion and future researc