KBS for Desktop PC Troubleshooting

Abstract: Background: In spite of the fact that computers continue to improve in speed and functions operation, they remain complex to use. Problems frequently happen, and it is hard to resolve or find solutions for them. This paper outlines the significance and feasibility of building a desktop PC problems diagnosis system. The system gathers problem symptoms from users’ desktops, rather than the user describes his/her problems to primary search engines. It automatically searches global databases of problem symptoms and solutions, and also allows ordinary users to contribute exact problem reports in a structured manner. Objectives: The main goal of this Knowledge Based System is to get the suitable problem desktop PC symptoms and the correct way to solve the errors. Methods: In this paper the design of the proposed Knowledge Based System which was produced to help users of desktop PC in knowing many of the problems and error such as : Power supply problems, CPU errors, RAM dumping error, hard disk errors and bad sectors and suddenly restarting PC. The proposed Knowledge Based System presents an overview about desktop PC hardware errors are given, the cause of fault are outlined and the solution to the problems whenever possible is given out. CLIPS Knowledge Based System language was used for designing and implementing the proposed expert system. Results: The proposed PC desktop troubleshooting Knowledge Based System was evaluated by IT students and they were satisfied with its performance

Conceptual design and feasibility evaluation model of a 10 to the 8th power bit oligatomic mass memory. Volume 1: Conceptual design

The oligatomic (mirror) thin film memory technology is a suitable candidate for general purpose spaceborne applications in the post-1975 time frame. Capacities of around 10 to the 8th power bits can be reliably implemented with systems designed around a 335 million bit module. The recommended mode was determined following an investigation of implementation sizes ranging from an 8,000,000 to 100,000,000 bits per module. Cost, power, weight, volume, reliability, maintainability and speed were investigated. The memory includes random access, NDRO, SEC-DED, nonvolatility, and dual interface characteristics. The applications most suitable for the technology are those involving a large capacity with high speed (no latency), nonvolatility, and random accessing

Brain Tumor Vascular Network Segmentation from Micro-Tomography

Micro-tomography produces high resolution images of bio- logical structures such as vascular networks. In this paper, we present a new approach for segmenting vascular network into pathological and normal regions from considering their micro-vessel 3D structure only. We define and use a condi- tional random field for segmenting the output of a watershed algorithm. The tumoral and normal classes are thus character- ized by their respective distribution of watershed region size interpreted as local vascular territories

Memory built-in self-repair and correction for improving yield: a review

Nanometer memories are highly prone to defects due to dense structure, necessitating memory built-in self-repair as a must-have feature to improve yield. Today’s system-on-chips contain memories occupying an area as high as 90% of the chip area. Shrinking technology uses stricter design rules for memories, making them more prone to manufacturing defects. Further, using 3D-stacked memories makes the system vulnerable to newer defects such as those coming from through-silicon-vias (TSV) and micro bumps. The increased memory size is also resulting in an increase in soft errors during system operation. Multiple memory repair techniques based on redundancy and correction codes have been presented to recover from such defects and prevent system failures. This paper reviews recently published memory repair methodologies, including various built-in self-repair (BISR) architectures, repair analysis algorithms, in-system repair, and soft repair handling using error correcting codes (ECC). It provides a classification of these techniques based on method and usage. Finally, it reviews evaluation methods used to determine the effectiveness of the repair algorithms. The paper aims to present a survey of these methodologies and prepare a platform for developing repair methods for upcoming-generation memories