Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

Modelling and analysis of crosstalk in scaled CMOS interconnects

The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in system

Characterisation of crosstalk defects in submicron CMOS VLSI interconnects

The main problem addressed in this research work is a crosstalk defect, which is defined as an unexpected signal change due to the coupling between signals or power lines. Here its characteristic under 3 proposed models is investigated to find whether such a noise could lead to real logic faults in IC systems. As a result, mathematical analysis for various bus systems was established, with 3 main factors found to determine the amount of crosstalk: i) how the input buffers are sized; ii) the physical arrangements of the tracks; and iii) the number of switching tracks involved. Minimum sizes of the width and separation lead to the highest crosstalk while increasing in the length does not contribute much variation. Higher level of crosstalk is also found in higher metal layers due mainly to the reduced capacitance to the substrate. The crosstalk is at its maximum when the track concerned is the middle track of a bus connected to a weak buffer while the other signal lines are switching. From this information, the worse-case analysis for various bus configurations is proposed for 0.7, 0.5 and 0.35 µ CMOS technologies. For most of conventional logic circuits, a crosstalk as large as about a half of the supply voltage is required if a fault is to occur. For the buffer circuits the level of crosstalk required depends very much on the transition voltage, which is in turn controlled by the sizing of its n and p MOS transistors forming the buffer. It is concluded that in general case if crosstalk can be kept to be no larger that 30% of the supply voltage the circuit can be said to be very reliable and virtually free from crosstalk fault. Finally test structures are suggested so that real measurements can be made to verify the simulation result

52 km-long transmission link using a 50 Gb/s O-band silicon microring modulator co-packaged with a 1V-CMOS driver

We present an O-band silicon microring modulator with up to 50 Gb/s modulation rates, co-packaged with a 1V-CMOS driver in a dispersion un-compensated, transmission experiment through 52 km of standard single-mode fiber. The experimental results show 10(-9) error-rate operation with a negligible power penalty of 0.2 dB for 40 Gb/s and wide-open eye diagrams for 50 Gb/s data, corresponding to a record high bandwidth-distance product of 2600 Gb.km/s. A comparative analysis between the proposed transmitter assembly and a commercial LiNbO3 modulator revealed a moderate increase of 3.8 dB in power penalty, requiring only 20% of the driving voltage level used by the commercial modulator