Path allocation in a three-stage broadband switch with intermediate channel grouping

A method for path allocation for use with three-stage ATM switches that feature multiple channels between the switch modules in adjacent stages is described. The method is suited to hardware implementation using parallelism to achieve a very short execution time. This allows path allocation to be performed anew in each time slot. A detailed description of the necessary hardware is presented. This hardware counts the number of cells requesting each output module, allocates a path through the intermediate stage of the switch to each cell, and generates a routing tag for each cell, indicating the path assigned to i

Blocking behaviors of crosstalk-free optical Banyan networks on vertical stacking

Banyan networks are attractive for constructing directional coupler (DC)-based optical switching networks for their small depth and self-routing capability. Crosstalk between optical signals passing through the same DC is an intrinsic drawback in DC-based optical networks. Vertical stacking of multiple copies of an optical banyan network is a novel scheme for building nonblocking (crosstalk-free) optical switching networks. The resulting network, namely vertically stacked optical banyan (VSOB) network, preserves all the properties of the banyan network, but increases the hardware cost significantly. Though much work has been done for determining the minimum number of stacked copies (planes) required for a nonblocking VSOB network, little is known on analyzing the blocking probabilities of VSOB networks that do not meet the nonblocking condition (i.e., with fewer stacked copies than required by the nonblocking condition). In this paper, we analyze the blocking probabilities of VSOB networks and develop their upper and lower bounds with respect to the number of planes in the networks. These bounds depict accurately the overall blocking behaviors of VSOB networks and agree with the conditions of strictly nonblocking and rearrangeably nonblocking VSOB networks respectively. Extensive simulation on a network simulator with both random routing and packing strategy has shown that the blocking probabilities of both strategies fall nicely within our bounds, and the blocking probability of packing strategy actually matches the lower bound. The proposed bounds are significant because they reveal the inherent relationships between blocking probability and network hardware cost in terms of the number of planes, and provide network developers a quantitative guidance to trade blocking probability for hardware cost. In particular, our bounds provide network designers an effective tool to estimate the minimum and maximum blocking probabilities of VSOB networks in which different routing strategies may be applied. An interesting conclusion drawn from our work that has practical applications is that the hardware cost of a VSOB network can be reduced dramatically if a predictable and almost negligible nonzero blocking probability is allowed.Xiaohong Jiang; Hong Shen; Khandker, Md.M.-ur-R.; Horiguchi, S

Optical computing: introduction by the guest editors to the feature in the 1 May 1988 issue

The feature in the 1 May 1988 issue of Applied Optics includes a collection of papers originally presented at the 1987 Lake Tahoe Topical Meeting on Optical Computing. These papers emphasize digital optical computing systems, optical interconnects, and devices for optical computing, but analog optical processing is considered as well

Multistage interconnection networks : improved routing algorithms and fault tolerance

Multistage interconnection networks for use by multiprocessor systems are optimal in terms of the number of switching element, but the routing algorithms used to set up these networks are suboptimal in terms of time. The network set-up time and reliability are the major factors to affect the performance of multistage interconnection networks. This work improves routing on Benes and Clos networks as well as the fault tolerant capability. The permutation representation is examined as well as the Clos and Benes networks. A modified edge coloring algorithm is applied to the regular bipartite multigraph which represents a Clos network. The looping and parallel looping algorithms are examined and a modified Tree-Connected Computer is adopted to execute a bidirectional parallel looping algorithm for Benes networks. A new fault tolerant Clos network is presented

An Aggregate Scalable Scheme for Expanding the Crossbar Switch Network; Design and Performance Analysis

New computer network topology, called Penta-S, is simulated. This network is built of cross bar switch modules. Each module connects 32 computer nodes. Each node has two ports, one connects the node to the crossbar switch module and the other connects the node to a correspondent client node in another module through a shuffle link. The performance of this network is simulated under various network sizes, packet lengths and loads. The results are compared with those obtained from Macramé project for Clos multistage interconnection network and 2D-Grid network. The throughput of Penta-S falls between the throughput of Clos and the throughput of 2D-Grid networks. The maximum throughput of Penta-S was obtained at packet length of 128 bytes. Also the throughput grows linearly with the network size. On the opposite of Clos and 2D-Grid networks, the per-node throughput of Penta-S improves as the network size grows. The per-packet latency proved to be better than that of Clos network for large packet lengths and high loads. Also the packet latency proved to be nearly constant against various loads. The cost-efficiency of Penta-S proved to be better than those of 2D-Grid and Clos networks for large number of nodes (>200 nodes in the case of 2D-Grid and >350 nodes in the case of Clos).On the opposite of other networks, the cost-efficiency of Penta-S grows as its size grows. So this topology suits large networks and high traffic loads