Preamble design using embedded signalling for OFDM broadcast systems based on reduced-complexity distance detection

The second generation digital terrestrial television broadcasting standard (DVB-T2) adopts the so-called P1 symbol as the preamble for initial synchronization. The P1 symbol also carries a number of basic transmission parameters, including the fast Fourier transform size and the single-input/single-output as well as multiple-input/single-output mode, in order to appropriately configure the receiver for carrying out the subsequent processing. In this contribution, an improved preamble design is proposed, where a pair of training sequences is inserted in the frequency domain and their distance is used for transmission parameter signalling. At the receiver, only a low-complexity correlator is required for the detection of the signalling. Both the coarse carrier frequency offset and the signalling can be simultaneously estimated by detecting the above-mentioned correlation. Compared to the standardised P1 symbol, the proposed preamble design significantly reduces the complexity of the receiver while retaining high robustness in frequency-selective fading channels. Furthermore, we demonstrate that the proposed preamble design achieves a better signalling performance than the standardised P1 symbol, despite reducing the numbers of multiplications and additions by about 40% and 20%, respectively

Design of multiplierless correlators for timing synchronization in IEEE 802.11a wireless LANs

Timing synchronization for IEEE 802.11a WLANs requires using a correlator to correlate the received signal with a known waveform. Straightforward implementation of this correlator results in the need to perform 320 million complex multiplications per second. This significant requirement can be eliminated by using multiplierless correlators. In this paper, multiplierless correlators are designed based on constraining the real and imaginary parts of correlator coefficients to be sums of powers of two. Sets of coefficients that yield good synchronization performance for simple A WGN channels are first identified; then their goodness for indoor communication environments is verified by simulation for multipath fading channels. Several multiplierless correlators are found. Comparison among these correlators identifies a good one that requires to perform only 26 addition/subtraction operations per correlator output while a similar synchronization performance can be maintained.published_or_final_versio

SYNCHRONIZATION AND RESOURCE ALLOCATION IN DOWNLINK OFDM SYSTEMS

The next generation (4G) wireless systems are expected to provide universal personal and multimedia communications with seamless connection and very high rate transmissions and without regard to the users’ mobility and location. OFDM technique is recognized as one of the leading candidates to provide the wireless signalling for 4G systems. The major challenges in downlink multiuser OFDM based 4G systems include the wireless channel, the synchronization and radio resource management. Thus algorithms are required to achieve accurate timing and frequency offset estimation and the efficient utilization of radio resources such as subcarrier, bit and power allocation. The objectives of the thesis are of two fields. Firstly, we presented the frequency offset estimation algorithms for OFDM systems. Building our work upon the classic single user OFDM architecture, we proposed two FFT-based frequency offset estimation algorithms with low computational complexity. The computer simulation results and comparisons show that the proposed algorithms provide smaller error variance than previous well-known algorithm. Secondly, we presented the resource allocation algorithms for OFDM systems. Building our work upon the downlink multiuser OFDM architecture, we aimed to minimize the total transmit power by exploiting the system diversity through the management of subcarrier allocation, adaptive modulation and power allocation. Particularly, we focused on the dynamic resource allocation algorithms for multiuser OFDM system and multiuser MIMO-OFDM system. For the multiuser OFDM system, we proposed a lowiv complexity channel gain difference based subcarrier allocation algorithm. For the multiuser MIMO-OFDM system, we proposed a unit-power based subcarrier allocation algorithm. These proposed algorithms are all combined with the optimal bit allocation algorithm to achieve the minimal total transmit power. The numerical results and comparisons with various conventional nonadaptive and adaptive algorithmic approaches are provided to show that the proposed resource allocation algorithms improve the system efficiencies and performance given that the Quality of Service (QoS) for each user is guaranteed. The simulation work of this project is based on hand written codes in the platform of the MATLAB R2007b

Sincronização de quadro e frequência para OFDM no padrão IEEE 802.15.4g : algoritmos e implementação em hardware

Orientadores: Renato da Rocha Lopes, Eduardo Rodrigues de LimaDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: O objetivo deste trabalho é propor métodos de sincronização de quadro e de frequência de portadora para a camada física MR-OFDM do padrão IEEE 802.15.4g, começando pela pesquisa de algoritmos, passando pelas etapas de modelagem e simulação em alto nível, e finalmente implementando e avaliando os métodos propostos em hardware. A sincronização de quadro é o processo responsável por detectar o início do dado transmitido, ou seja, a primeira amostra válida do sinal de interesse. No caso de sistemas OFDM, onde o sinal transmitido é composto por um ou mais símbolos OFDM (cada símbolo sendo composto por uma quantidade fixa de amostras), o objetivo é detectar a borda ou janelamento de tais símbolos OFDM, ou seja, onde começa e termina cada um deles. A sincronização de frequência, por sua vez, consiste em estimar e compensar o erro de frequência de portadora, causado principalmente pelo descasamento dos osciladores do transmissor e do receptor. Com base em estudos preliminares, selecionamos o algoritmo de Minn para a detecção de quadro. Para a correção de erro de frequência, dividimos o processo em duas etapas, como é geralmente proposto na literatura: primeiro, o erro de frequência fracionário é estimado no domínio do tempo durante a detecção de quadro e compensado via rotação de sinal; após a conversão do domínio do tempo para o domínio da frequência, o erro de frequência inteiro é estimado e compensado utilizando um novo e simples algoritmo que será proposto e detalhado neste trabalho. Os algoritmos propostos foram implementados em hardware e uma plataforma de verificação baseada em FPGA foi criada para avaliar o seu desempenho. Os módulos implementados são parte de um projeto que está sendo desenvolvido no Instituto de Pesquisa Eldorado (Campinas) que tem como objetivo implementar em ASIC um transceptor compatível com o padrão IEEE 802.15.4gAbstract: The objective of this work is proposing methods of frame and frequency synchronization for the MR-OFDM PHY of IEEE 802.15.4g standard, starting with the research of state-of-the-art algorithms, passing through modeling, high-level simulations, and finally implementing and evaluating the proposed methods in hardware. Frame synchronization is the process responsible for detecting the beginning of transmitted data and, in the case of OFDM systems, the border of each OFDM symbol, while frequency synchronization consists of estimating and compensating the Carrier Frequency Offset (CFO) caused mainly by a mismatch between the transmitter and receiver oscillators. Based on the initial studies, we selected Minn¿s algorithm for frame detection. For the CFO correction, we split the process into two steps, as commonly proposed in the literature: first, the Fractional CFO is estimated in the time domain during the frame detection and compensated via signal rotation; after the conversion from time to frequency domain, the Integer CFO is estimated and compensated with a novel and simple algorithm that will be detailed in this work. The proposed algorithms were implemented in hardware and inserted in an FPGA-based verification platform for performance measurement. The implemented modules are part of a project that is under development at Eldorado Research Institute (Campinas) and aims to implement in ASIC a transceiver compliant to the IEEE 802.15.4g standardMestradoTelecomunicações e TelemáticaMestra em Engenharia Elétric

WIMAX TESTBED

WiMAX, the Worldwide Interoperability for Microwave Access, is a telecommunications technology aimed at providing wireless data over long distances in a variety of ways, from point-to-point links to full mobile cellular type access. It is based on the IEEE 802.16 standard, which is also called Wire IessMAN. The name WiMAX was created by the WiMAX Forum, which was formed in June 2001 to promote conformance and interoperability of the standard. The forum describes WiMAX as a standards-based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. This Final Year Project attempts to simulate via Simulink, the working mechanism of a WiMAX testbed that includes a transmitter, channel and receiver. This undertaking will involve the baseband physical radio link. Rayleigh channel model together with frequency and timing offsets are introduced to the system and a blind receiver will attempt to correct these offsets and provide channel equalization. The testbed will use the Double Sliding Window for timing offset synchronization and the Schmid! & Cox algorithm for Fractional Frequency Offset estimation. The Integer Frequency Offset synchronization is achieved via correlation of the incoming preamble with its local copy whereas Residual Carrier Fr~quency Offset is estimated using the L th extension method. A linear Channel Estimator is added and combined with all the other blocks to form the testbed. From the results, this testbed matches the standard requirements for the BER when SNR is 18dB or higher. At these SNRs, the receiver side of the testbed is successful in performing the required synchronization and obtaining the same data sent. Sending data with SNR lower than 18dB compromises its performance as the channel equalizer is non-linear. This project also takes the first few steps of hardware implementation by using Real Time Workshop to convert the Simulink model into C codes which run outside MATLAB. In addition, the Double Sliding Window and Schmid! & Cox blocks are converted to Xilinx blocks and proven to be working like their Simulink counterparts