Modeling EMI Resulting from a Signal Via Transition Through Power/Ground Layers

Signal transitioning through layers on vias are very common in multi-layer printed circuit board (PCB) design. For a signal via transitioning through the internal power and ground planes, the return current must switch from one reference plane to another reference plane. The discontinuity of the return current at the via excites the power and ground planes, and results in noise on the power bus that can lead to signal integrity, as well as EMI problems. Numerical methods, such as the finite-difference time-domain (FDTD), Moment of Methods (MoM), and partial element equivalent circuit (PEEC) method, were employed herein to study this problem. The modeled results are supported by measurements. In addition, a common EMI mitigation approach of adding a decoupling capacitor was investigated with the FDTD method

Readout and Control Beyond a Few Qubits: Scaling-up Solid State Quantum Systems

Quantum entanglement and superposition, in addition to revealing interesting physics in their own right, can be harnessed as computational resources in a machine, enabling a range of algorithms for classically intractable problems. In recent years, experiments with small numbers of qubits have been demonstrated in a range of solid-state systems, but this is far from the numbers required to realise a useful quantum computer. In addition to the qubits themselves, quantum operation requires a host of classical electronics for control and readout, and current techniques used in few-qubit systems are not scalable. This thesis presents a series of techniques for control and readout of solid-state qubits, working towards scalability by integrating classical control with the quantum technology. Two techniques for reducing the footprint associated with readout of gallium arsenide spin qubits are demonstrated. Gate electrodes, used to define the quantum dot, are also shown to be sensitive state detectors. These gate-sensors, and the more conventional Quantum Point Contacts, are then multiplexed in the frequency domain, where three-channel qubit readout and ten-channel QPC readout are demonstrated. Two types of superconducting devices are also explored. The loss in superconducting coplanar waveguide resonators is measured, and a suppression of coupling to the parasitic electromagnetic environment is demonstrated. The thesis also details software for the simulation of Josephson-junction based circuits including features beyond what is available in commercial products. Finally, an architecture for managing control of a scalable machine is proposed where classical components are distributed throughout a cryostat and cryogenic switches route control pulses to the appropriate qubits. A simple implementation of the architecture is demonstrated that incorporates a double quantum dot, a gallium arsenide switch matrix, frequency multiplexed readout, and cryogenic classical computation

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

On Co-Optimization Of Constrained Satisfiability Problems For Hardware Software Applications

Manufacturing technology has permitted an exponential growth in transistor count and density. However, making efficient use of the available transistors in the design has become exceedingly difficult. Standard design flow involves synthesis, verification, placement and routing followed by final tape out of the design. Due to the presence of various undesirable effects like capacitive crosstalk, supply noise, high temperatures, etc., verification/validation of the design has become a challenging problem. Therefore, having a good design convergence may not be possible within the target time, due to a need for a large number of design iterations. Capacitive crosstalk is one of the major causes of design convergence problems in deep sub-micron era. With scaling, the number of crosstalk violations has been increasing because of reduced inter-wire distances. Consequently only the most severe crosstalk faults are fixed pre-silicon while the rest are tested post-silicon. Testing for capacitive crosstalk involves generation of input patterns which can be applied post-silicon to the integrated circuit and comparison of the output response. These patterns are generated at the gate/ Register Transfer Level (RTL) of abstraction using Automatic Test Pattern Generation (ATPG) tools. In this dissertation, anInteger Linear Programming (ILP) based ATPG technique for maximizing crosstalk induced delay increase at the victim net, for multiple aggressor crosstalk faults, is presented. Moreover, various solutions for pattern generation considering both zero as well as unit delay models is also proposed. With voltage scaling, power supply switching noise has become one of the leading causes of signal integrity related failures in deep sub-micron designs. Hence, during power supply network design and analysis of power supply switching noise, computation of peak supply current is an essential step. Traditional peak current estimation approaches involve addition of peak current associated with all the CMOS gates which are switching in a combinational circuit. Consequently, this approach does not take the Boolean and temporal relationships of the circuit into account. This work presents an ILP based technique for generation of an input pattern pair which maximizes switching supply currents for a combinational circuit in the presence of integer gate delays. The input pattern pair generated using the above approach can be applied post-silicon for power droop testing. With high level of integration, Multi-Processor Systems on Chip (MPSoC) feature multiple processor cores and accelerators on the same die, so as to exploit the instruction level parallelism in the application. For hardware-software co-design, application programming model is based on a Task Graph, which represents task dependencies and execution/transfer times for various threads and processes within an application. Mapping an application to an MPSoC traditionally involves representing it in the form of a task graph and employing static scheduling in order to minimize the schedule length. Dynamic system behavior is not taken into consideration during static scheduling, while dynamic scheduling requires the knowledge of task graph at runtime. A run-time task graph extraction heuristic to facilitate dynamic scheduling is also presented here. A novel game theory based approach uses this extracted task graph to perform run-time scheduling in order to minimize total schedule length. With increase in transistor density, power density has gone up substantially. This has lead to generation of regions with very high temperature called Hotspots. Hotspots lead to reliability and performance issues and affect design convergence. In current generation Integrated Circuits (ICs) temperature is controlled by reducing power dissipation using Dynamic Thermal Management (DTM) techniques like frequency and/or voltage scaling. These techniques are reactive in nature and have detrimental effects on performance. Here, a look-ahead based task migration technique is proposed, in order to utilize the multitude of cores available in an MPSoC to eliminate thermal emergencies. Our technique is based on temperature prediction, leveraging upon a novel wavelet based thermal modeling approach. Hence, this work addresses several optimization problems that can be reduced to constrained max-satisfiability, involving integer as well as Boolean constraints in hardware and software domains. Moreover, it provides domain specific heuristic solutions for each of them

Optimal Control of Scalable Quantum Devices

Superconducting quantum bits are integrated circuits operated at Milli\-kelvin temperatures and rely on Josephson junctions as their key element. They allow fast operations through standard room-temperature microwave electronics and cryogenic cooling and are currently pursed for the realization of universal quantum computers. In this thesis we use optimal control methods to improve the performance of quantum gates in scalable architectures consisting of transmon qubits. We show how to apply a multi-qubit gate for quantum simulation efficiently, use digital basis functions to reduce the number of pulse parameters in the optimization and simulate the effects of decoherence for analytical pulse shapes performing a perfect entangling gate. The main part focuses on tailoring and applying optimal control methods for an on-chip integration of the control circuitry with the superconducting qubit. This borrows ideas and devices developed in the field of superconducting conventional computers, and we use optimal control with only a single-bit of amplitude resolution to find trains of pulses for fast quantum gates, derive reasonable system parameters and extract conditions for analytic pulse trains. This has the potential to reduce the wiring of microwave control lines and the overall heat load on the chip, allowing for easier scalability when the number of qubits continues to grow.Supraleitende Qubits sind elektrische Schaltkreise die im Millikelvin- Temperaturbereich betrieben werden und auf Josephson-Kontakten basieren. Sie erlauben schnelle Operationen mittels herkömmlicher Mikrowellenelektronik und Tieftemperaturkühlung und sind ein Kandidat für die Realisierung eines universellen Quantencomputers. In dieser Arbeit verwenden wir Methoden der optimalen Steuerung um die Leistung von Quantengattern in skalierbaren Transmonqubit-Architekturen zu verbessern. Wir zeigen wie ein Multiqubitgatter für die Quantensimulation effizient angewendet wird, nutzten digitale Basisfunktionen um die Anzahl der Pulsparameter in der Optimierung zu reduzieren und simulieren Dekohärenzeffekte für analytische Pulsformen eines perfekten Verschränkers. Das Hauptgewicht der Arbeit liegt auf der Anpassung und Anwendung optimaler Steuerungsmethoden für die Integration des Steuerungsschaltkreises mit dem supraleitende Qubit auf einem gemeinsamen Chip. Unter Verwendung von Ideen und Bauteilen aus dem Gebiet der supraleitenden konventionellen Computer nutzen wir optimale Steuerung mit nur einem Bit an Amplitudenauflösung um Pulssequenzen für schnelle Quantengatter zu finden, leiten realisierbare Systemparameter ab und sowie Bedingungen für analytische Pulssequenzen. Dies hat das Potenzial die Verkabelung der Mikrowellensteuerung und die gesamte Wärmeentwicklung auf dem Chip zu reduzieren und erlaubt eine einfache Skalierbarkeit wenn die Anzahl der Qubits weiter wächst

Optimal Control of Scalable Quantum Devices

Superconducting quantum bits are integrated circuits operated at Milli\-kelvin temperatures and rely on Josephson junctions as their key element. They allow fast operations through standard room-temperature microwave electronics and cryogenic cooling and are currently pursed for the realization of universal quantum computers. In this thesis we use optimal control methods to improve the performance of quantum gates in scalable architectures consisting of transmon qubits. We show how to apply a multi-qubit gate for quantum simulation efficiently, use digital basis functions to reduce the number of pulse parameters in the optimization and simulate the effects of decoherence for analytical pulse shapes performing a perfect entangling gate. The main part focuses on tailoring and applying optimal control methods for an on-chip integration of the control circuitry with the superconducting qubit. This borrows ideas and devices developed in the field of superconducting conventional computers, and we use optimal control with only a single-bit of amplitude resolution to find trains of pulses for fast quantum gates, derive reasonable system parameters and extract conditions for analytic pulse trains. This has the potential to reduce the wiring of microwave control lines and the overall heat load on the chip, allowing for easier scalability when the number of qubits continues to grow.Supraleitende Qubits sind elektrische Schaltkreise die im Millikelvin- Temperaturbereich betrieben werden und auf Josephson-Kontakten basieren. Sie erlauben schnelle Operationen mittels herkömmlicher Mikrowellenelektronik und Tieftemperaturkühlung und sind ein Kandidat für die Realisierung eines universellen Quantencomputers. In dieser Arbeit verwenden wir Methoden der optimalen Steuerung um die Leistung von Quantengattern in skalierbaren Transmonqubit-Architekturen zu verbessern. Wir zeigen wie ein Multiqubitgatter für die Quantensimulation effizient angewendet wird, nutzten digitale Basisfunktionen um die Anzahl der Pulsparameter in der Optimierung zu reduzieren und simulieren Dekohärenzeffekte für analytische Pulsformen eines perfekten Verschränkers. Das Hauptgewicht der Arbeit liegt auf der Anpassung und Anwendung optimaler Steuerungsmethoden für die Integration des Steuerungsschaltkreises mit dem supraleitende Qubit auf einem gemeinsamen Chip. Unter Verwendung von Ideen und Bauteilen aus dem Gebiet der supraleitenden konventionellen Computer nutzen wir optimale Steuerung mit nur einem Bit an Amplitudenauflösung um Pulssequenzen für schnelle Quantengatter zu finden, leiten realisierbare Systemparameter ab und sowie Bedingungen für analytische Pulssequenzen. Dies hat das Potenzial die Verkabelung der Mikrowellensteuerung und die gesamte Wärmeentwicklung auf dem Chip zu reduzieren und erlaubt eine einfache Skalierbarkeit wenn die Anzahl der Qubits weiter wächst

Electromagnetic Interference and Compatibility

Recent progress in the fields of Electrical and Electronic Engineering has created new application scenarios and new Electromagnetic Compatibility (EMC) challenges, along with novel tools and methodologies to address them. This volume, which collects the contributions published in the “Electromagnetic Interference and Compatibility” Special Issue of MDPI Electronics, provides a vivid picture of current research trends and new developments in the rapidly evolving, broad area of EMC, including contributions on EMC issues in digital communications, power electronics, and analog integrated circuits and sensors, along with signal and power integrity and electromagnetic interference (EMI) suppression properties of materials

Special Topics in Information Technology

This open access book presents thirteen outstanding doctoral dissertations in Information Technology from the Department of Electronics, Information and Bioengineering, Politecnico di Milano, Italy. Information Technology has always been highly interdisciplinary, as many aspects have to be considered in IT systems. The doctoral studies program in IT at Politecnico di Milano emphasizes this interdisciplinary nature, which is becoming more and more important in recent technological advances, in collaborative projects, and in the education of young researchers. Accordingly, the focus of advanced research is on pursuing a rigorous approach to specific research topics starting from a broad background in various areas of Information Technology, especially Computer Science and Engineering, Electronics, Systems and Control, and Telecommunications. Each year, more than 50 PhDs graduate from the program. This book gathers the outcomes of the thirteen best theses defended in 2020-21 and selected for the IT PhD Award. Each of the authors provides a chapter summarizing his/her findings, including an introduction, description of methods, main achievements and future work on the topic. Hence, the book provides a cutting-edge overview of the latest research trends in Information Technology at Politecnico di Milano, presented in an easy-to-read format that will also appeal to non-specialists

Special Topics in Information Technology

This open access book presents thirteen outstanding doctoral dissertations in Information Technology from the Department of Electronics, Information and Bioengineering, Politecnico di Milano, Italy. Information Technology has always been highly interdisciplinary, as many aspects have to be considered in IT systems. The doctoral studies program in IT at Politecnico di Milano emphasizes this interdisciplinary nature, which is becoming more and more important in recent technological advances, in collaborative projects, and in the education of young researchers. Accordingly, the focus of advanced research is on pursuing a rigorous approach to specific research topics starting from a broad background in various areas of Information Technology, especially Computer Science and Engineering, Electronics, Systems and Control, and Telecommunications. Each year, more than 50 PhDs graduate from the program. This book gathers the outcomes of the thirteen best theses defended in 2020-21 and selected for the IT PhD Award. Each of the authors provides a chapter summarizing his/her findings, including an introduction, description of methods, main achievements and future work on the topic. Hence, the book provides a cutting-edge overview of the latest research trends in Information Technology at Politecnico di Milano, presented in an easy-to-read format that will also appeal to non-specialists