Binning for IC Quality: Experimental Studies on the SEMATECH Data

The earlier smaller bipolar study did not provide a high enough bin 0 population to directly observe test escapes and thereby estimate defect levels for the best bin. Results presented here indicate that the best bin can be reasonably expected to show a 2 - 5 factor improvement in defect levels over the average for the lot for moderate to high yields (the overall yield for these experiments was approximately 65%). The experiments also confirm the dependence of the best bin quality on test transparency. The defect level improvement is poorer for the case Of IDDQ escapes where the tests applied had a much higher escape rate. Overall experimental results are consistent with analytical projections for typical values of the clustering parameter in [9]. The final version of this paper will include extensive analysis to validate the analytical models based on this data

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

Interconnect yield analysis and fault tolerance for field programmable gate arrays

Imperial Users onl

Improving timing verification and delay testing methodologies for IC designs

textThe task of ensuring the correct temporal behavior of IC designs, both before and after fabrication, is extremely important. It is becoming even more imperative as the demand for performance increases and process technology advances into the deep sub-micron region. This dissertation tackles the key issues in the timing verification and delay testing methodologies. An efficient methodology is presented to identify false timing paths in the timing verification methodology which utilizes ATPG technique and timing information from an ordered list of timing paths according to the delay information. This dissertation also presents a speed binning methodology which utilizes structural delay tests successfully instead of functional tests. In addition, it establishes a methodology which quantifies the correlation between the timing verification prediction and actual silicon measurement of timing paths. This quantification methodology lays the foundation for further research to study the impact of deep submicron effects on design performanceElectrical and Computer Engineerin

Cross-Layer Pathfinding for Off-Chip Interconnects

Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects

0.18?m high performance CMOS process optimization

Complementary metal oxide semiconductor (CMOS) is the most widely used discrete structure in the semiconductor sector. Low static power consumption, full-rail high/low voltage transfer characteristics as well as its ease of scaling creates the perfect combination for the high performance integrated circuits (IC). Today’s challenging semiconductor industry profile brings the deadlines earlier than expected as a result of the shorter time-to- market plans as well as limited lifetime on sophisticated ICs. Process optimization for manufacturability is one of the most challenging issues in the semiconductor industry since the adoption of the sub-micron CMOS technology. Process technologies often times gets released with- in tight project schedules without jeopardizing the quality and customer’s trust. Manufacturing facilities often times institute very strict process controls in order to achieve the quality and the high yields. At the same time they take the financial burden of throwing away the nonconforming material which does not meet the ir specifications. Improving the device performance becomes the responsibility of the Integration/Device engineering through a series of process characterization studies. This paper outlines the various 0.18 μm. CMOS technology issues such as threshold voltage and saturation current control, and proposes methods to optimize the process through a series of characterization studies. 6-Sigma-DMAIC process was explored in order to achieve the desired goal. Techniques described in this thesis could be used in any manufacturing or development environment