24,016 research outputs found
Modeling the Impact of Process Variation on Resistive Bridge Defects
Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridges. This paper presents a fast and accurate technique to model the effect of process variation on resistive bridge defects. The proposed model is implemented in two stages: firstly, it employs an accurate transistor model (BSIM4) to calculate the critical resistance of a bridge; secondly, the effect of process variation is incorporated in this model by using three transistor parameters: gate length (L), threshold voltage (V) and effective mobility (ueff) where each follow Gaussian distribution. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 7 times faster and in the worst case, error in bridge critical resistance is 0.8% when compared with HSPICE
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Testing of mixed-signal systems using dynamic stimuli
The impulse response of a linear circuit element contains enough information to functionally characterise that element. A technique for comparison of observed and expected (reference) transient responses, which results in an absolute measure of device functionality, is presented. Comparisons of transient response test results with the results from existing test programs are also presented
Towards Structural Testing of Superconductor Electronics
Many of the semiconductor technologies are already\ud
facing limitations while new-generation data and\ud
telecommunication systems are implemented. Although in\ud
its infancy, superconductor electronics (SCE) is capable of\ud
handling some of these high-end tasks. We have started a\ud
defect-oriented test methodology for SCE, so that reliable\ud
systems can be implemented in this technology. In this\ud
paper, the details of the study on the Rapid Single-Flux\ud
Quantum (RSFQ) process are presented. We present\ud
common defects in the SCE processes and corresponding\ud
test methodologies to detect them. The (measurement)\ud
results prove that we are able to detect possible random\ud
defects for statistical purposes in yield analysis. This\ud
paper also presents possible test methodologies for RSFQ\ud
circuits based on defect oriented testing (DOT)
Metastability-Containing Circuits
In digital circuits, metastability can cause deteriorated signals that
neither are logical 0 or logical 1, breaking the abstraction of Boolean logic.
Unfortunately, any way of reading a signal from an unsynchronized clock domain
or performing an analog-to-digital conversion incurs the risk of a metastable
upset; no digital circuit can deterministically avoid, resolve, or detect
metastability (Marino, 1981). Synchronizers, the only traditional
countermeasure, exponentially decrease the odds of maintained metastability
over time. Trading synchronization delay for an increased probability to
resolve metastability to logical 0 or 1, they do not guarantee success.
We propose a fundamentally different approach: It is possible to contain
metastability by fine-grained logical masking so that it cannot infect the
entire circuit. This technique guarantees a limited degree of metastability
in---and uncertainty about---the output.
At the heart of our approach lies a time- and value-discrete model for
metastability in synchronous clocked digital circuits. Metastability is
propagated in a worst-case fashion, allowing to derive deterministic
guarantees, without and unlike synchronizers. The proposed model permits
positive results and passes the test of reproducing Marino's impossibility
results. We fully classify which functions can be computed by circuits with
standard registers. Regarding masking registers, we show that they become
computationally strictly more powerful with each clock cycle, resulting in a
non-trivial hierarchy of computable functions
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level
In recent technology nodes, reliability is considered a part of the standard design ¿ow at all levels of embedded system design. While techniques that use only low-level models at gate- and register transfer-level offer high accuracy, they are too inefficient to consider the overall application of the embedded system. Multi-level models with high abstraction are essential to efficiently evaluate the impact of physical defects on the system. This paper provides a methodology that leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This way it is possible to accurately evaluate the impact of the faults on the entire hardware/software system. A case study of a system consisting of hardware and software for image compression and data encryption is presented and the method is compared to a standard gate/RT mixed-level approac
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