Layout regularity metric as a fast indicator of process variations

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations

Investigating block mask lithography variation using finite-difference time-domain simulation

Simulation work has long been realized as a method for analyzing semiconductor processing expediently and cost-effectively. As technology advancements strive to meet increasingly stringent parameter constraints, difficult issues arise. In this paper, challenges in block mask lithography will be discussed with the aid of using simulation packages developed by Panoramic Technology®. Halo formation utilizes a 20-30° tilt-angle implantation [1]. The block mask defines the geometries of the resist opening to allow implantation of atoms to extend into the channel region. Due to designed resolution scaling and tolerance in conjunction with substrate topography, there can be undesired influence on the electrical device characteristics due to block variations. Although the block mask pattern definition is relatively simple, additional investigation is required to understand the sensitivities that drive the implant resist CD variation. In this study, block mask measurements processed using 248 nm and 193 nm illumination sources were used to calibrate the simulation work. Addition of optical proximity correction (OPC) and wafer topography geometry parameters have been shown to improve modeling capabilities. The modeling work was also able to show the benefits of a developable bottom anti-reflection coating (dBARC) process over a single layer resist (SLR) process in the resist intensity profiles as gate pitch is decreased. The goal of this work was to develop an accurate simulation model that characterizes the lithographic performance needed to support the transition into future technology nodes

Performance optimization for gridded-layout standard cells

The grid placement of contacts and gates enables more effective use of resolution enhancement techniques, which in turn allow a reduction of critical dimensions. Although the regular placement adds restrictions during cell layout, the overall circuit area can be made smaller and the extra manufacturing cost can be kept to the lowest by a careful selection of the grid pitch, using template-trim lithography method, allowing random contact placement in the vertical direction, and using rectangular rather than square contacts. The purpose of this work is to optimize the gridded-layout-based process. The trade-off between the layout area and manufacturing cost, and the determination of the minimum grid pitch are discussed in this paper. We demonstrate that it is a 1-D scaling instead of the conventional 2-D scaling for standard cells and the narrow MOSFETs inside after the application of the gridded layout on the contact and gate levels. The corresponding effects on circuit performances, including the leakage current, are also explored.published_or_final_versio

Evanescent wave assist features for optical projection lithography

Evanescent Wave Assist Features (EWAFs) are features that are sensitive to near-field radiation that modify diffracted order intensities from photomask patterns. In implementations studied in this thesis, the EWAFs increase a transmitting feature\u27s image contrast and Normalized Image Log Slope (NILS). In this way, the EWAFs are a way to improve image fidelity for high-resolution features. The assist features consist of local, buried grooves located around transmitting mask regions. These grooves reside in otherwise unused areas, since they are located under or on top of opaque mask absorber regions. In these buried locations, they are not optically visible to the lithographic system in a traditional sense. Designs are explored for both top-surface and bottom-surface EWAFs on 1-D and 2-D layouts. Using EWAFs, 27% image contrast improvements have been shown on contact layouts, as well as best-case image contrast improvements of over 2X on 1-D slot-type mask layouts. Dependence of EWAF effect on mask absorber material and bottom-surface relief shape is studied, as well as polarization sensitivity and the role of Surface Plasmon Polaritons (SPP). TM polarized light creates a normal-component field enhancement that amplifies surface waves across suitably conductive absorbers. These waves can then interact with bottom-surface EWAF grooves, and convert to propagating based on grating action. The converted orders may then interact with standard transmitted orders from a transmission feature, resulting in enhancement or suppression, depending on EWAF tone, pitch regime, and illumination angle. A demonstration EWAF sample, as well as a reference sample with no grooves, was fabricated at the RIT SMFL and tested using a Variable Angle Spectroscopic Ellipsometer (VASE). Accounting for pitch deviations during fabrication, as well as lateral inter-layer alignment offsets gives diffracted order responses that agree with SPP resonances observed in the samples at normal incidence and diffracted order enhancement factors that agree with simulation

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface