Structured Mapping of Petri Net States and Events for FPGA Implementations

The paper presents a new method of structured encoding of global internal states and events in Reconfigurable Logic Controllers, which are directly mapped into Field Programmable Gate Arrays (FPGA). Modular, concurrently decomposed, colored state machine is chosen as a intermediate model, before the mapping of Petri net into an array structure of dedicated but very flexible and reliable digital system. The initial textual specification in formal Gentzen logic serves both as a design description for a rapid prototyping, as well as formal model, suitable for detailed computer-based reasoning about optimized and synthesized logic controller, implemented in configurable hardware. Only the selected linear subset from general, universal propositional Gentzen Logic is necessary to deduce several properties of the net, such as relations of nonconcurrency among structurally ordered macroplaces. The goal of this paper is to present the design methodology for modeling and synthesis of discrete controllers using related Petri net theory, rule-based theory (mathematical logic), and VHDL

Implementation of Algorithm of Petri Nets Distributed Synthesis into FPGA

In the paper an implementation of algorithm of Petri net array-based synthesis is presented. The method is based on decomposition of colored interpreted macro Petri net into subnets. The structured encoding of places in subnets is done of using minimal numbers of bits. Microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. This algorithm is implemented in C# and delivered as a stand alone library

Transition based synthesis with modular encoding of Petri nets into FPGAs

The paper describes a new method for the synthesis of the application specific logic controllers, targeted into the FPGA. The initial steps of the proposed control algorithm rely on the notion of a Petri net, which is an easy way to describe parallel processes. The algorithm is oriented on transition based logic description. It allows easy analysis of dynamics and functioning of the circuit. The logic circuit is also decomposed into logic blocks responsible for particular functions. It leads to the compact implementation with usage of different kind of logic elements like. Additionally such decomposition allows easy analysis of circuit

Application of hypergraphs in decomposition of discrete systems

seria: Lecture Notes in Control and Computer Science ; vol. 23

On the use of programming languages for textual specification of Petri Net Models

O presente artigo revê e aprofunda o artigo intitulado Towards a Human-Friendly Textual Language for Petri Nets, apresentado no Workshop on Petri Net Standards 2007.As a general interchange format for Petri net models, the Petri Net Markup Language (PNML) allows the specification of Petri net models for all Petri net classes. Those models are typically generated by graphical editors for each Petri net type. Yet, there is no general way to specify Petri net models in a human-friendly textual notation. Instead of proposing a standard for such textual notation, this paper proposes the use of popular general purpose programming languages for the creation and modification of net models defined using PNML. To that end, the paper presents a model for the concepts, and the respective inter- relations, that should be available to define Petri net models in a compact textual format. After, it presents a general framework to specify model composition, using node fusion, for any Petri net class. The framework allows the specification of node fusions and node refinements based on the specification of fusions for each node and net label. The labels’ fusions are defined through the implementation of an abstract data type for the respective Petri net type definition. This allows a general support for model structuring, where several well-known graphical conveniences, e.g. node references and synchronous channels, can be supported and seen as particular cases

Partial Reconfiguration in the Field of Logic Controllers Design

The paper presents method for logic controllers multi context implementation by means of partial reconfiguration. The UML state machine diagram specifies the behaviour of the logic controller. Multi context functionality is specified at the specification level as variants of the composite state. Each composite state, both orthogonal or compositional, describes specific functional requirement of the control process. The functional decomposition provided by composite states is required by the dynamic partial reconfiguration flow. The state machines specified by UML state machine diagrams are transformed into hierarchical configurable Petri nets (HCfgPN). HCfgPN are a Petri nets variant with the direct support of the exceptions handling mechanism. The paper presents placesoriented method for HCfgPN description in Verilog language. In the paper proposed methodology was illustrated by means of simple industrial control process

An evolutionary approach to the use of Petri net based models: from parallel controllers to HW/SW co-design

"A workshop within the 19th International Conference on Applications and Theory of Petri Nets - ICATPN’1998"The main purpose of this article is to present how Petri Nets (PNs) have been used for hardware design at our research laboratory. We describe the use of PN models to specify synchronous parallel controllers and how PN speci cations can be extended to include the behavioural description of the data path, by using object-oriented concepts. Some hierarchical mechanisms which deal with the speci cation of complex digital systems are highlighted. It is described a design flow that includes, among others, the automatic generation of VHDL code to synthesize the control unit of the system. The use of PNs as part of a multiple-view model within an object-oriented methodology for hardware/software codesign is debated. The EDgAR-2 platform is considered as the recon gurable target architecture for implementing the systems and its main characteristics are shown

Approximation methods for stochastic petri nets

Stochastic Marked Graphs are a concurrent decision free formalism provided with a powerful synchronization mechanism generalizing conventional Fork Join Queueing Networks. In some particular cases the analysis of the throughput can be done analytically. Otherwise the analysis suffers from the classical state explosion problem. Embedded in the divide and conquer paradigm, approximation techniques are introduced for the analysis of stochastic marked graphs and Macroplace/Macrotransition-nets (MPMT-nets), a new subclass introduced herein. MPMT-nets are a subclass of Petri nets that allow limited choice, concurrency and sharing of resources. The modeling power of MPMT is much larger than that of marked graphs, e.g., MPMT-nets can model manufacturing flow lines with unreliable machines and dataflow graphs where choice and synchronization occur. The basic idea leads to the notion of a cut to split the original net system into two subnets. The cuts lead to two aggregated net systems where one of the subnets is reduced to a single transition. A further reduction leads to a basic skeleton. The generalization of the idea leads to multiple cuts, where single cuts can be applied recursively leading to a hierarchical decomposition. Based on the decomposition, a response time approximation technique for the performance analysis is introduced. Also, delay equivalence, which has previously been introduced in the context of marked graphs by Woodside et al., Marie's method and flow equivalent aggregation are applied to the aggregated net systems. The experimental results show that response time approximation converges quickly and shows reasonable accuracy in most cases. The convergence of Marie's method and flow equivalent aggregation are applied to the aggregated net systems. The experimental results show that response time approximation converges quickly and shows reasonable accuracy in most cases. The convergence of Marie's is slower, but the accuracy is generally better. Delay equivalence often fails to converge, while flow equivalent aggregation can lead to potentially bad results if a strong dependence of the mean completion time on the interarrival process exists

An evolutionary approach to the use of petri net based models : from parallel controllers to Hw/Sw codesign

The main purpose of this article is to present how Petri Nets (PNs) have been used for hardware design at our research laboratory. We describe the use of PN models to specify synchronous parallel controllers and how PN specifications can be extended to include the behavioural description of the data path, by using object-oriented concepts. Some hierarchical mechanisms which deal with the specification of complex digital systems are highlighted. It is described a design flow that includes, among others, the automatic generation of VHDL code to synthesize the control unit of the system. The use of PNs as part of a multiple-view model within an object-oriented methodology for hardware/software codesign is debated. The EDgAR-2 platform is considered as the reconfigurable target architecture for implementing the systems and its main characteristics are shown