3,736 research outputs found

    A hierarchical architecture for increasing efficiency of large photovoltaic plants under non-homogeneous solar irradiation

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    Under non-homogeneous solar irradiation, photovoltaic (PV) panels receive different solar irradiance, resulting in a decrease in efficiency of the PV generation system. There are a few technical options to fix this issue that goes under the name of mismatch. One of these is the reconfiguration of the PV generation system, namely changing the connections of the PV panels from the initial configuration to the optimal one. Such technique has been widely considered for small systems, due to the excessive number of required switches. In this paper, the authors propose a new method for increasing the efficiency of large PV systems under non-homogeneous solar irradiation using Series-Parallel (SP) topology. In the first part of the paper, the authors propose a method containing two key points: a switching matrix to change the connection of PV panels based on SP topology and the proof that the SP-based reconfiguration method can increase the efficiency of the photovoltaic system up to 50%. In the second part, the authors propose the extension of the method proposed in the first part to improve the efficiency of large solar generation systems by means of a two-levels architecture to minimize the cost of fabrication of the switching matrix

    Coarse-grained reconfigurable array architectures

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    Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code

    Run-time resource management in fault-tolerant network on reconfigurable chips

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    Non-power-of-Two FFTs: Exploring the Flexibility of the Montium TP

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    Coarse-grain reconfigurable architectures, like the Montium TP, have proven to be a very successful approach for low-power and high-performance computation of regular digital signal processing algorithms. This paper presents the implementation of a class of non-power-of-two FFTs to discover the limitations and Flexibility of the Montium TP for less regular algorithms. A non-power-of-two FFT is less regular compared to a traditional power-of-two FFT. The results of the implementation show the processing time, accuracy, energy consumption and Flexibility of the implementation
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