A 3-D Track-Finding Processor for the CMS Level-1 Muon Trigger

We report on the design and test results of a prototype processor for the CMS Level-1 trigger that performs 3-D track reconstruction and measurement from data recorded by the cathode strip chambers of the endcap muon system. The tracking algorithms are written in C++ using a class library we developed that facilitates automatic conversion to Verilog. The code is synthesized into firmware for field-programmable gate-arrays from the Xilinx Virtex-II series. A second-generation prototype has been developed and is currently under test. It performs regional track-finding in a 60 degree azimuthal sector and accepts 3 GB/s of input data synchronously with the 40 MHz beam crossing frequency. The latency of the track-finding algorithms is expected to be 250 ns, including geometrical alignment correction of incoming track segments and a final momentum assignment based on the muon trajectory in the non-uniform magnetic field in the CMS endcaps.Comment: 7 pages, 5 figures, proceedings for the conference on Computing in High Energy and Nuclear Physics, March 24-28 2003, La Jolla, Californi

Reusable Automated Agent For Universal Verification Methodology System Testbench

Pre-silicon verification process is an important cog in an application specific integrated chip design cycle. It is considered one of the biggest bottle-neck in modern day design projects. Thus, verification efficiency and productivity has gained a lot of attention lately and will be the driving factor of this research. The purpose of this research is to build a verification solution that actively promotes reusability and interoperability of verification components and improve the automation within the verification solution. These are identified as important concepts to improve verification efficiency and productivity. A state of the art UVM (Universal Verification Methodology) verification solution centered on these concepts is built for the sideband module of a hard memory controller. First, the verification requirements of the sideband module are investigated. Next, existing testbench solutions were evaluated for its reuse capabilities. This is followed by proposing and implementing a testbench architecture that highly reuses existing verification components and be reused friendly itself. Next, the architecture is improved to allow higher level of automation within the testbench. The implemented verification solution is then measured and analysed for its reusability and automation. The result obtained shows the implemented verification solution achieves a reusability of 21.70% in a system level testbench and 49.67% in the standalone sideband verification environment. In addition, the autonomous agent approach implemented in the architecture reduces the test writer's burden by at least 60% and up to 78%

Are IEEE 1500 compliant cores really compliant to the standard?

Functional verification of complex SoC designs is a challenging task, which fortunately is increasingly supported by automation. This article proposes a verification component for IEEE Std 1500, to be plugged into a commercial verification tool suit

A Technical Road Map from System Verilog to UVM

As the fabrication technology is advancing more logic is being placed on a silicon die which makes verification more challenging task than ever. More than 70% of the design cycle is used for verification. To improve the time to market we need a reusable verification environment that detects all functional errors and avoid re-spin. Universal verification methodology was introduced to fulfill these goals. UVM is well structured, reusable with little or no modifications, do not interfere with the device under test (DUT) and gives the speed of verification. UVM is supported by all major simulator vendors, which was not in earlier methodologies. This methodology provides a standard unified solution that compiles on all tools. This paper introduces the advantages of UVM over System Verilog, basic terminologies used in UVM and a simple functional verification environment construction using UVM DOI: 10.17762/ijritcc2321-8169.15038

The Art of Fault Injection

Classical greek philosopher considered the foremost virtues to be temperance, justice, courage, and prudence. In this paper we relate these cardinal virtues to the correct methodological approaches that researchers should follow when setting up a fault injection experiment. With this work we try to understand where the "straightforward pathway" lies, in order to highlight those common methodological errors that deeply influence the coherency and the meaningfulness of fault injection experiments. Fault injection is like an art, where the success of the experiments depends on a very delicate balance between modeling, creativity, statistics, and patience

Design of SPI(Serial Peripheral Interface) Protocol with DO-254 Compliance

The objective is to design the SPI protocol compliant with avionic hardware design standards (D0-254). This is to make sure that the protocol follows the most stringent standards so as to develop a fool proof design that would be highly reliable and would not fail under conventional circumstances. The significance of this project is designing the Serial Peripheral Interface (SPI) protocol in the DO-254 flow which is an industry standard used for the hardware process. Using DO-254 standards SPI is coded in Verilog. Single Master-Single Slave, Independent Slave configuration, Daisy Chain configuration all the three designs are designed following the rule sets of DO254. It is verified using the assertion based verification (ABV) or System Verilog Assertions (SVA)

Chaining Test Cases for Reactive System Testing (extended version)

Testing of synchronous reactive systems is challenging because long input sequences are often needed to drive them into a state at which a desired feature can be tested. This is particularly problematic in on-target testing, where a system is tested in its real-life application environment and the time required for resetting is high. This paper presents an approach to discovering a test case chain---a single software execution that covers a group of test goals and minimises overall test execution time. Our technique targets the scenario in which test goals for the requirements are given as safety properties. We give conditions for the existence and minimality of a single test case chain and minimise the number of test chains if a single test chain is infeasible. We report experimental results with a prototype tool for C code generated from Simulink models and compare it to state-of-the-art test suite generators.Comment: extended version of paper published at ICTSS'1

Design of Complex Multiplier Using Vedic Mathematics

In this project, a 4x4 multiplier is implemented that utilizes the Urdhava Tiryakbhyam sutra method in Vedic mathematics. This method is applicable in all two decimal number multiplications which offers high speed calculation and improved efficiency. Thus, the design of a 4x4 Vedic-based multiplier is solely aimed at performing faster multiplications and achieving quicker processing speeds than the traditional multipliers. The architecture of the Vedic multiplier consists of four 2x2 multipliers and three adders of different bit sizes that are assembled using the Wallace tree implementation. The coding for the multipliers and adders is written in Verilog Hardware Description Language (HDL) in the Quartus Prime 17 Software. Functional simulation is then carried out to ensure that the Vedic multiplier performs the accurate multiplication operations, while the Verilog Compiled Simulator is employed to compile and simulate the multiplier design. Following this, the Design Compiler (DC) and Integrated Circuit Compiler (ICC) command scripts are then composed to allow the logic and physical synthesis to be performed on the Vedic and traditional multipliers. From there, the performance level of both these multipliers are assessed through reference to several key parameters such as timing, area, power consumption, overflow percentage and congestion statistics. Based on the results obtained in the synthesis process, the Vedic multiplier possesses faster operational speed than the traditional multiplier (due to a shorter processing time), but ultimately exhibits a greater power consumption and wider area coverage. &nbsp

Design of Complex Multiplier Using Vedic Mathematics

In this project, a 4x4 multiplier is implemented that utilizes the Urdhava Tiryakbhyam sutra method in Vedic mathematics. This method is applicable in all two decimal number multiplications which offers high speed calculation and improved efficiency. Thus, the design of a 4x4 Vedic-based multiplier is solely aimed at performing faster multiplications and achieving quicker processing speeds than the traditional multipliers. The architecture of the Vedic multiplier consists of four 2x2 multipliers and three adders of different bit sizes that are assembled using the Wallace tree implementation. The coding for the multipliers and adders is written in Verilog Hardware Description Language (HDL) in the Quartus Prime 17 Software. Functional simulation is then carried out to ensure that the Vedic multiplier performs the accurate multiplication operations, while the Verilog Compiled Simulator is employed to compile and simulate the multiplier design. Following this, the Design Compiler (DC) and Integrated Circuit Compiler (ICC) command scripts are then composed to allow the logic and physical synthesis to be performed on the Vedic and traditional multipliers. From there, the performance level of both these multipliers are assessed through reference to several key parameters such as timing, area, power consumption, overflow percentage and congestion statistics. Based on the results obtained in the synthesis process, the Vedic multiplier possesses faster operational speed than the traditional multiplier (due to a shorter processing time), but ultimately exhibits a greater power consumption and wider area coverage. &nbsp