5 research outputs found

    DSL-based triple-play services

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    This research examines the triple play service based on the ADSL technology. The voice over IP will be checked and combined with the internet data by two monitoring programs in order to examine the performance that this service offers and then will be compared with the usual method of internet connection.This research examines the triple play service based on the ADSL technology. The voice over IP will be checked and combined with the internet data by two monitoring programs in order to examine the performance that this service offers and then will be compared with the usual method of internet connection.

    Resilient Cell Resequencing in Terabit Routers

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    Multistage interconnection networks with internal cell buffering and dynamic routing are among the most cost-effective architectures for multi-terabit internet routers. One of the key design issues for such systems is maintaining cell ordering, since cells are subject to varying delays as they pass through the interconnection network. The most flexible and scalable approach to cell resequencing uses timestamps and a time-ordered resequencing buffer at each router output port. Conventional, fixed-threshold resequencers can perform poorly in the presence of extreme traffic conditions. This paper explores alternative resequencer designs that are more tolerant of such traffic. These alternatives include a novel adaptive resequencer that adjusts the time cells spend waiting in the resequencing buffer, based on the recent history of the interconnection network delay. The design is straightforward to implement and requires only constant time per cell, making it suitable for systems with link speeds of up to 40 Gb/s. We show that the combination of adaptive resequencing and appropriately designed inter-connection networks can limit resequencing errors to negligible levels without requiring large resequencing latencies

    Design and implementation of a functional WATM test bed to study the performance of handoff schemes

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    Includes bibliographical references.The focus of this research is on the design and implementation of a WATM functional architecture in order to facilitate a seamless handoff. The project includes an experimental implementation of the WATM network. This required the building of a prototype WATM network with existing ATM switches and implementing handover protocol schemes at both the access and network sides

    Novel techniques in large scaleable ATM switches

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    Bibliography: p. 172-178.This dissertation explores the research area of large scale ATM switches. The requirements for an ATM switch are determined by overviewing the ATM network architecture. These requirements lead to the discussion of an abstract ATM switch which illustrates the components of an ATM switch that automatically scale with increasing switch size (the Input Modules and Output Modules) and those that do not (the Connection Admission Control and Switch Management systems as well as the Cell Switch Fabric). An architecture is suggested which may result in a scalable Switch Management and Connection Admission Control function. However, the main thrust of the dissertation is confined to the cell switch fabric. The fundamental mathematical limits of ATM switches and buffer placement is presented next emphasising the desirability of output buffering. This is followed by an overview of the possible routing strategies in a multi-stage interconnection network. A variety of space division switches are then considered which leads to a discussion of the hypercube fabric, (a novel switching technique). The hypercube fabric achieves good performance with an O(N.log₂N)²) scaling. The output module, resequencing, cell scheduling and output buffering technique is presented leading to a complete description of the proposed ATM switch. Various traffic models are used to quantify the switch's performance. These include a simple exponential inter-arrival time model, a locality of reference model and a self-similar, bursty, multiplexed Variable Bit Rate (VBR) model. FIFO queueing is simple to implement in an ATNI switch, however, more responsive queueing strategies can result in an improved performance. An associative memory is presented which allows the separate queues in the ATM switch to be effectively logically combined into a single FIFO queue. The associative memory is described in detail and its feasibility is shown by laying out the Integrated Circuit masks and performing an analogue simulation of the IC's performance is SPICE3. Although optimisations were required to the original design, the feasibility of the approach is shown with a 15Ƞs write time and a 160Ƞs read time for a 32 row, 8 priority bit, 10 routing bit version of the memory. This is achieved with 2µm technology, more advanced technologies may result in even better performance. The various traffic models and switch models are simulated in a number of runs. This shows the performance of the hypercube which outperforms a Clos network of equivalent technology and approaches the performance of an ideal reference fabric. The associative memory leverages a significant performance advantage in the hypercube network and a modest advantage in the Clos network. The performance of the switches is shown to degrade with increasing traffic density, increasing locality of reference, increasing variance in the cell rate and increasing burst length. Interestingly, the fabrics show no real degradation in response to increasing self similarity in the fabric. Lastly, the appendices present suggestions on how redundancy, reliability and multicasting can be achieved in the hypercube fabric. An overview of integrated circuits is provided. A brief description of commercial ATM switching products is given. Lastly, a road map to the simulation code is provided in the form of descriptions of the functionality found in all of the files within the source tree. This is intended to provide the starting ground for anyone wishing to modify or extend the simulation system developed for this thesis

    Designing a large scale switch interconnection architecture and a study of ATM scheduling algorithms.

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    by Yee Ka Chi.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 101-[106]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.1.1 --- Large Scale Switch Interconnections --- p.2Chapter 1.1.2 --- Multichannel Switching and Resequencing --- p.6Chapter 1.1.3 --- Scheduling --- p.7Chapter 2 --- Hierarchical Banyan Switch Interconnection --- p.12Chapter 2.1 --- Introduction --- p.12Chapter 2.2 --- Switch Architecture --- p.13Chapter 2.3 --- Switch Operation --- p.19Chapter 2.3.1 --- Call Setup --- p.19Chapter 2.3.2 --- Cell Routing --- p.21Chapter 2.3.3 --- Fault Tolerance --- p.27Chapter 2.4 --- Call Blocking Analysis --- p.28Chapter 2.4.1 --- Dilated Banyan --- p.29Chapter 2.4.2 --- Dilated Benes Network --- p.30Chapter 2.4.3 --- HBSI --- p.30Chapter 2.5 --- Results and Discussions --- p.31Chapter 2.6 --- Summary --- p.37Chapter 3 --- Multichannel Switching and Resequencing --- p.40Chapter 3.1 --- Introduction --- p.40Chapter 3.2 --- Channel Assignment --- p.41Chapter 3.2.1 --- VC-Based Channel Allocation Mechanism --- p.41Chapter 3.2.2 --- Port-Based Channel Allocation Mechanism --- p.45Chapter 3.2.3 --- Trunk-Based Channel Allocation Mechanism --- p.46Chapter 3.3 --- Resequencer --- p.50Chapter 3.3.1 --- Resequencing Algorithm --- p.50Chapter 3.4 --- Results and Discussion --- p.55Chapter 3.5 --- Summary --- p.60Chapter 4 --- Scheduling --- p.62Chapter 4.1 --- Introduction --- p.62Chapter 4.2 --- Virtual Clock Scheduling (VCS) --- p.62Chapter 4.3 --- Gated Virtual Clock Scheduling (GVCS) --- p.70Chapter 4.4 --- Time-Priority Model --- p.75Chapter 4.5 --- Programmable Rate-based Scheduler (PRS) --- p.80Chapter 4.6 --- Integration with Resequencer --- p.83Chapter 4.7 --- Results and Discussions --- p.86Chapter 4.8 --- Summary --- p.96Chapter 5 --- Conclusion --- p.99Bibliography --- p.10
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