Design, optimization and Real Time implementation of a new Embedded Chien Search Block for Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes on FPGA Board

The development of error correcting codes has been a major concern for communications systems. Therefore, RS and BCH (Reed-Solomon and Bose, Ray-Chaudhuri and Hocquenghem) are effective methods to improve the quality of digital transmission. In this paper a new algorithm of Chien Search block for embedded systems is proposed. This algorithm is based on a factorization of error locator polynomial. i.e, we can minimize an important number of logic gates and hardware resources using the FPGA card. Consequently, it reduces the power consumption with a percentage which can reach 40 % compared to the basic RS and BCH decoder. The proposed system is designed, simulated using the hardware description language (HDL) and Quartus development software. Also, the performance of the designed embedded Chien search block for decoder RS\BCH (255, 239) has been successfully verified by implementation on FPGA board

FPGA based Novel High Speed DAQ System Design with Error Correction

Present state of the art applications in the area of high energy physics experiments (HEP), radar communication, satellite communication and bio medical instrumentation require fault resilient data acquisition (DAQ) system with the data rate in the order of Gbps. In order to keep the high speed DAQ system functional in such radiation environment where direct intervention of human is not possible, a robust and error free communication system is necessary. In this work we present an efficient DAQ design and its implementation on field programmable gate array (FPGA). The proposed DAQ system supports high speed data communication (~4.8 Gbps) and achieves multi-bit error correction capabilities. BCH code (named after Raj Bose and D. K. RayChaudhuri) has been used for multi-bit error correction. The design has been implemented on Xilinx Kintex-7 board and is tested for board to board communication as well as for board to PC using PCIe (Peripheral Component Interconnect express) interface. To the best of our knowledge, the proposed FPGA based high speed DAQ system utilizing optical link and multi-bit error resiliency can be considered first of its kind. Performance estimation of the implemented DAQ system is done based on resource utilization, critical path delay, efficiency and bit error rate (BER).Comment: ISVLSI 2015. arXiv admin note: substantial text overlap with arXiv:1505.04569, arXiv:1503.0881

PERANCANGAN SANDI BCH (15,7) BERBASIS FPGA SPARTAN-3E DAN DELPHI 7

BCH (Bose, Chauduri, Hocquenghem) codes is a channel codes that can be used as an error control coding that works in galois field. BCH codes can correct errors that occur in the process of transmitting data in digital communication system. BCH codes is a channel coding which capable to correcting errors depend on two parameters that are codeword length of n and word information length of k In this final project will be designed BCH codes with parameter values n = 15 and k = 7 which can correct maximum of two errors. The purpose of this research is to design BCH (J5,7) encoder system based on VHDL which is implemented in Xilinx Spartan 3E XC3S500E FPGA and to design BCH (J5,7) decoder system based on Delphi 7 software. The process of adding an error into codeword is simulated with ATMega8535 microcontroller. Codeword which is already contains two errors, will be transmitted to a personal computer (PC) through ATMega8535 microcontroller and RS-232 serial cable. Furthermore, the BCH (J5,7) decoder system based on Delphi 7, will be corrected this codeword. Implementation of BCH (15.7) encoder using 40 slices or J% of the total capacity of slices, 46 LUTs or J% of the total capacity of LUT and 2 J lOBs or 9% of total capacity lOB XC3S500E Spartan -3E FPGA. This research shows that this design can work well, any 2 bits error in some position of I 5 bits has been corrected

A parallel Viterbi decoder for block cyclic and convolution codes

We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has restricted complexity in that the number of communications to or from any processor cannot exceed 4 for BCH codes. The resulting algorithm works in lock step making it suitable for implementation on a systolic processor array, which we have implemented on a field programmable gate array and demonstrate the perfect scaling of the algorithm for two exemplar BCH codes. The parallelisation strategy is applicable to all cyclic codes and convolution codes. We also present a novel method for generating the state transition diagrams for these codes

Efficient Decoder for Optical Transport Networks Achieving Near Capacity Performance

Today’s optical transport networks (OTNs) support a plethora of services such as video streaming, cloud computing, social networking and many more. To make such a wide assortment of services possible, a tremendous amount of data needs to be carried over the internet backbone supported by these optical transport networks. In order to cope with this increase in traffic, data rate on OTNs has increased significantly. Product codes (PC) are a class of codes that provide good coding gain at reasonable decoding complexity and, hence, have been a popular choice for OTNs in recent times. The key goal of this thesis is to implement a decoder for a Product Code (PC) on a Virtex7 Field Programmable Gate Array(FPGA). The product code of choice for this project is based on a (1023,993) BCH code as a component code. The conventional decoder for BCH codes has a computationally expensive step for finding the roots of error locator polynomial. The BCH decoder implemented as a part of this project is optimized to speed up the decoding process while at the same time also simplifying the hardware complexity of the design. The implementation is parallelized and pipelined to achieve high throughputs. This provides a hardware platform to evaluate the performance of product codes at low bit error rates that is infeasible using software simulations