NDE: An effective approach to improved reliability and safety. A technology survey

Technical abstracts are presented for about 100 significant documents relating to nondestructive testing of aircraft structures or related structural testing and the reliability of the more commonly used evaluation methods. Particular attention is directed toward acoustic emission; liquid penetrant; magnetic particle; ultrasonics; eddy current; and radiography. The introduction of the report includes an overview of the state-of-the-art represented in the documents that have been abstracted

Miniaturised SH EMATs for fast robotic screening of wall thinning in steel plates

Electromagnetic acoustic transducers (EMATs) are well suited to generating and detecting a variety of different ultrasonic wavemodes, without the need for couplant, and they can be operated through some coatings. EMATs can be used to generate shear horizontal (SH) waves, which show promise for fast screening of wall thinning and other defects. However, commercial SH-wave EMATs are not suitable for robotic implementation on ferritic steel due to the large magnetic drag force from the magnets. This article describes the design and characterisation of miniaturised SH guided wave EMATs, which significantly reduce the magnetic drag and enable mounting onto a small crawler robot for sample scanning. The performance of the miniaturised EMATs is characterised and compared to a commercial EMAT. It is shown that signal to noise ratio is reduced, but remains within an acceptable range to use on steel. The bandwidth and directivity are increased, depending on the exact design used. Their ability to detect flat bottomed holes mimicking wall thinning is also tested

Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results

Design-for-delay-testability techniques for high-speed digital circuits

The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud getting more and more important

Second Conference on NDE for Aerospace Requirements

Nondestructive evaluation and inspection procedures must constantly improve rapidly in order to keep pace with corresponding advances being made in aerospace material and systems. In response to this need, the 1989 Conference was organized to provide a forum for discussion between the materials scientists, systems designers, and NDE engineers who produce current and future aerospace systems. It is anticipated that problems in current systems can be resolved more quickly and that new materials and structures can be designed and manufactured in such a way as to be more easily inspected and to perform reliably over the life cycle of the system

Friction Stir Welding Manufacturing Advancement by On-Line High Temperature Phased Array Ultrasonic Testing and Correlation of Process Parameters to Joint Quality

Welding, a manufacturing process for joining, is widely employed in aerospace, aeronautical, maritime, nuclear, and automotive industries. Optimizing these techniques are paramount to continue the development of technologically advanced structures and vehicles. In this work, the manufacturing technique of friction stir welding (FSW) with aluminum alloy (AA) 2219-T87 is investigated to improve understanding of the process and advance manufacturing efficiency. AAs are widely employed in aerospace applications due to their notable strength and ductility. The extension of good strength and ductility to cryogenic temperatures make AAs suitable for rocket oxidizer and fuel tankage. AA-2219, a descendent of the original duralumin used to make Zeppelin frames, is currently in wide use in the aerospace industry. FSW, a solid-state process, joins the surfaces of a seam by stirring the surfaces together with a pin while the metal is held in place by a shoulder. The strength and ductility of friction stir (FS) welds depends upon the weld parameters, chiefly spindle rotational speed, feedrate, and plunge force (pinch force for self-reacting welds). Between conditions that produce defects, it appears in this study as well as those studies of which we are aware that FS welds show little variation in strength; however, outside this process parameter “window” the weld strength drops markedly. Manufacturers operate within this process parameter window, and the parameter establishment phase of welding operations constitutes the establishment of this process parameter window. The work herein aims to improve the manufacturing process of FSW by creating a new process parameter window selection methodology, creation of a weld quality prediction model, developing an analytical defect suppression model, and constructing a high temperature on-line phased array ultrasonic testing system for quality inspection

Hardware Fault Injection

Hardware fault injection is the widely accepted approach to evaluate the behavior of a circuit in the presence of faults. Thus, it plays a key role in the design of robust circuits. This chapter presents a comprehensive review of hardware fault injection techniques, including physical and logical approaches. The implementation of effective fault injection systems is also analyzed. Particular emphasis is made on the recently developed emulation-based techniques, which can provide large flexibility along with unprecedented levels of performance. These capabilities provide a way to tackle reliability evaluation of complex circuits.Publicad

Marshall Space Flight Center Research and Technology Report 2019

Today, our calling to explore is greater than ever before, and here at Marshall Space Flight Centerwe make human deep space exploration possible. A key goal for Artemis is demonstrating and perfecting capabilities on the Moon for technologies needed for humans to get to Mars. This years report features 10 of the Agencys 16 Technology Areas, and I am proud of Marshalls role in creating solutions for so many of these daunting technical challenges. Many of these projects will lead to sustainable in-space architecture for human space exploration that will allow us to travel to the Moon, on to Mars, and beyond. Others are developing new scientific instruments capable of providing an unprecedented glimpse into our universe. NASA has led the charge in space exploration for more than six decades, and through the Artemis program we will help build on our work in low Earth orbit and pave the way to the Moon and Mars. At Marshall, we leverage the skills and interest of the international community to conduct scientific research, develop and demonstrate technology, and train international crews to operate further from Earth for longer periods of time than ever before first at the lunar surface, then on to our next giant leap, human exploration of Mars. While each project in this report seeks to advance new technology and challenge conventions, it is important to recognize the diversity of activities and people supporting our mission. This report not only showcases the Centers capabilities and our partnerships, it also highlights the progress our people have achieved in the past year. These scientists, researchers and innovators are why Marshall and NASA will continue to be a leader in innovation, exploration, and discovery for years to come

Design for pre-bond testability in 3D integrated circuits

In this dissertation we propose several DFT techniques specific to 3D stacked IC systems. The goal has explicitly been to create techniques that integrate easily with existing IC test systems. Specifically, this means utilizing scan- and wrapper-based techniques, two foundations of the digital IC test industry. First, we describe a general test architecture for 3D ICs. In this architecture, each tier of a 3D design is wrapped in test control logic that both manages tier test pre-bond and integrates the tier into the large test architecture post-bond. We describe a new kind of boundary scan to provide the necessary test control and observation of the partial circuits, and we propose a new design methodology for test hardcore that ensures both pre-bond functionality and post-bond optimality. We present the application of these techniques to the 3D-MAPS test vehicle, which has proven their effectiveness. Second, we extend these DFT techniques to circuit-partitioned designs. We find that boundary scan design is generally sufficient, but that some 3D designs require special DFT treatment. Most importantly, we demonstrate that the functional partitioning inherent in 3D design can potentially decrease the total test cost of verifying a circuit. Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm co-designs the pre-bond and post-bond wrappers to simultaneously minimize test time and routing cost. On average, our algorithm utilizes over 90% of the wires in both the pre-bond and post-bond wrappers. Finally, we look at the 3D vias themselves to develop a low-cost, high-volume pre-bond test methodology appropriate for production-level test. We describe the shorting probes methodology, wherein large test probes are used to contact multiple small 3D vias. This technique is an all-digital test method that integrates seamlessly into existing test flows. Our experimental results demonstrate two key facts: neither the large capacitance of the probe tips nor the process variation in the 3D vias and the probe tips significantly hinders the testability of the circuits. Taken together, this body of work defines a complete test methodology for testing 3D ICs pre-bond, eliminating one of the key hurdles to the commercialization of 3D technology.PhDCommittee Chair: Lee, Hsien-Hsin; Committee Member: Bakir, Muhannad; Committee Member: Lim, Sung Kyu; Committee Member: Vuduc, Richard; Committee Member: Yalamanchili, Sudhaka