Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard

This paper addresses the implementation of Reed- Solomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the Digital Media Broadcasting (DMB). The most critical element of the Reed-Solomon algorithm is implemented on two different reconfigurable hardware architectures: an FPGA and a coarse-grained architecture: the Montium, The remaining parts are executed on an ARM processor. The results of this research show that a co-design of the ARM together with an FPGA or a Montium leads to a substantial decrease in energy consumption. The energy consumption of syndrome calculation of the Reed- Solomon decoding algorithm is estimated for an FPGA and a Montium by means of simulations. The Montium proves to be more efficient

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

High Performance Power Spectrum Analysis Using a FPGA Based Reconfigurable Computing Platform

Power-spectrum analysis is an important tool providing critical information about a signal. The range of applications includes communication-systems to DNA-sequencing. If there is interference present on a transmitted signal, it could be due to a natural cause or superimposed forcefully. In the latter case, its early detection and analysis becomes important. In such situations having a small observation window, a quick look at power-spectrum can reveal a great deal of information, including frequency and source of interference. In this paper, we present our design of a FPGA based reconfigurable platform for high performance power-spectrum analysis. This allows for the real-time data-acquisition and processing of samples of the incoming signal in a small time frame. The processing consists of computation of power, its average and peak, over a set of input values. This platform sustains simultaneous data streams on each of the four input channels.Comment: 5 pages, 3 figures. Published in the Proceedings of the IEEE International conference on Reconfigurable Computing and FPGAs (ReConFig 2006). Article also available at http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4100006&isnumber=409995

A novel architecture for a reconfigurable micro machining cell

There is a growing demand for machine tools that are specifically designed for the manufacture of micro-scale components. Such machine tools are integrated into flexible micro-manufacturing systems. Design objectives for such tools include energy efficiency, small footprint and importantly flexibility, with the ability to easily reconfigure the manufacturing system in response to process requirements and product demands. Such systems find application in medical, photonics, automotive and electronic industries. In this paper, a new architecture for a reconfigurable micro manufacturing system is presented. The proposed architecture comprises a micro manufacturing cell with the key design feature being a hexagonal-base on which three tool heads can be attached to three of its sides. Each such machine-tool head, or processing module, is able to perform a different manufacturing process. These tool heads are interchangeable, enabling the cell to be configured to process a wide range of components with different materials, dimensions, tolerances and specification. Additional components of the cell include manipulation robots and an automated buffer unit. Such cells can be integrated into a manufacturing system via a modular conveyor belt to transfer parts from one cell to another and into assembly. A key consideration of the architecture is a control system that is also modular and reconfigurable; such that when new processing modules are introduced the control system is aware of the change and adjusts accordingly. Further to this coordination, issues between modules and machining cells are also considered. Other design considerations include work-piece holding and manipulation. This paper provides an overview of the architecture, the key design and implementation challenges as well as a high level operational performance assessment by means of a discrete event simulation model of the micro factory cell

A low cost reconfigurable soft processor for multimedia applications: design synthesis and programming model

This paper presents an FPGA implementation of a low cost 8 bit reconfigurable processor core for media processing applications. The core is optimized to provide all basic arithmetic and logic functions required by the media processing and other domains, as well as to make it easily integrable into a 2D array. This paper presents an investigation of the feasibility of the core as a potential soft processing architecture for FPGA platforms. The core was synthesized on the entire Virtex FPGA family to evaluate its overall performance, scalability and portability. A special feature of the proposed architecture is its simple programming model which allows low level programming. Throughput results for popular benchmarks coded using the programming model and cycle accurate simulator are presented

A committee machine gas identification system based on dynamically reconfigurable FPGA

This paper proposes a gas identification system based on the committee machine (CM) classifier, which combines various gas identification algorithms, to obtain a unified decision with improved accuracy. The CM combines five different classifiers: K nearest neighbors (KNNs), multilayer perceptron (MLP), radial basis function (RBF), Gaussian mixture model (GMM), and probabilistic principal component analysis (PPCA). Experiments on real sensors' data proved the effectiveness of our system with an improved accuracy over individual classifiers. Due to the computationally intensive nature of CM, its implementation requires significant hardware resources. In order to overcome this problem, we propose a novel time multiplexing hardware implementation using a dynamically reconfigurable field programmable gate array (FPGA) platform. The processing is divided into three stages: sampling and preprocessing, pattern recognition, and decision stage. Dynamically reconfigurable FPGA technique is used to implement the system in a sequential manner, thus using limited hardware resources of the FPGA chip. The system is successfully tested for combustible gas identification application using our in-house tin-oxide gas sensors