Periodic binary sequence generators: VLSI circuits considerations

Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree

A Comparative Study of Some Pseudorandom Number Generators

We present results of an extensive test program of a group of pseudorandom number generators which are commonly used in the applications of physics, in particular in Monte Carlo simulations. The generators include public domain programs, manufacturer installed routines and a random number sequence produced from physical noise. We start by traditional statistical tests, followed by detailed bit level and visual tests. The computational speed of various algorithms is also scrutinized. Our results allow direct comparisons between the properties of different generators, as well as an assessment of the efficiency of the various test methods. This information provides the best available criterion to choose the best possible generator for a given problem. However, in light of recent problems reported with some of these generators, we also discuss the importance of developing more refined physical tests to find possible correlations not revealed by the present test methods.Comment: University of Helsinki preprint HU-TFT-93-22 (minor changes in Tables 2 and 7, and in the text, correspondingly

Design study of a HEAO-C spread spectrum transponder telemetry system for use with the TDRSS subnet

The results of a design study of a spread spectrum transponder for use on the HEAO-C satellite were given. The transponder performs the functions of code turn-around for ground range and range-rate determination, ground command receiver, and telemetry data transmitter. The spacecraft transponder and associated communication system components will allow the HEAO-C satellite to utilize the Tracking and Data Relay Satellite System (TDRSS) subnet of the post 1978 STDN. The following areas were discussed in the report: TDRSS Subnet Description, TDRSS-HEAO-C System Configuration, Gold Code Generator, Convolutional Encoder Design and Decoder Algorithm, High Speed Sequence Generators, Statistical Evaluation of Candidate Code Sequences using Amplitude and Phase Moments, Code and Carrier Phase Lock Loops, Total Spread Spectrum Transponder System, and Reference Literature Search

Reconfigurable elliptic curve cryptography

Elliptic Curve Cryptosystems (ECC) have been proposed as an alternative to other established public key cryptosystems such as RSA (Rivest Shamir Adleman). ECC provide more security per bit than other known public key schemes based on the discrete logarithm problem. Smaller key sizes result in faster computations, lower power consumption and memory and bandwidth savings, thus making ECC a fast, flexible and cost-effective solution for providing security in constrained environments. Implementing ECC on reconfigurable platform combines the speed, security and concurrency of hardware along with the flexibility of the software approach. This work proposes a generic architecture for elliptic curve cryptosystem on a Field Programmable Gate Array (FPGA) that performs an elliptic curve scalar multiplication in 1.16milliseconds for GF (2163), which is considerably faster than most other documented implementations. One of the benefits of the proposed processor architecture is that it is easily reprogrammable to use different algorithms and is adaptable to any field order. Also through reconfiguration the arithmetic unit can be optimized for different area/speed requirements. The mathematics involved uses binary extension field of the form GF (2n) as the underlying field and polynomial basis for the representation of the elements in the field. A significant gain in performance is obtained by using projective coordinates for the points on the curve during the computation process

Iterative message-passing-based algorithms to detect spreading codes

This thesis tackles the issue of the rapid acquisition of spreading codes in Direct-Sequence Spread-Spectrum (DS/SS) communication systems. In particular, a new algorithm is proposed that exploits the experience of the iterative decoding of modern codes (LDPC and turbo codes) to detect these sequences. This new method is a Message-Passing-based algorithm. Specifically, instead of correlating the received signal with local replicas of the transmitted linear feedback shift register (LFSR) sequence, an iterative Message-Passing algorithm is implemented to be run on a loopy graph. In particular, these graphical models are designed by manipulating the generating polynomial structure of the considered LFSR sequence. Therefore, this contribution is a detailed analysis of the detection technique based on Message-Passing algorithms to acquire m-Sequences and Gold codes. More in detail, a unified treatment to design and implement a specific set of graphical models for these codes is reported. A theoretical study on the acquisition time performance and their comparison to the standard algorithms (full-parallel, simple-serial, and hybrid searches) is done. A preliminary architectural design is also provided. Finally, the analysis is also enriched by comparing this new technique to the standard algorithms in terms of computational complexity and (missed/wrong/correct) acquisition probabilities as derived by simulations

Low Complexity Finite Field Multiplier for a New Class of Fields

Finite fields is considered as backbone of many branches in number theory, coding theory, cryptography, combinatorial designs, sequences, error-control codes, and algebraic geometry. Recently, there has been considerable attention over finite field arithmetic operations, specifically on more efficient algorithms in multiplications. Multiplication is extensively utilized in almost all branches of finite fields mentioned above. Utilizing finite field provides an advantage in designing hardware implementation since the ground field operations could be readily converted to VLSI design architecture. Moreover, due to importance and extensive usage of finite field arithmetic in cryptography, there is an obvious need for better and more efficient approach in implementation of software and/or hardware using different architectures in finite fields. This project is intended to utilize a newly found class of finite fields in conjunction with the Mastrovito algorithm to compute the polynomial multiplication more efficiently

A new approach in building parallel finite field multipliers

A new method for building bit-parallel polynomial basis finite field multipliers is proposed in this thesis. Among the different approaches to build such multipliers, Mastrovito multipliers based on a trinomial, an all-one-polynomial, or an equally-spacedpolynomial have the lowest complexities. The next best in this category is a conventional multiplier based on a pentanomial. Any newly presented method should have complexity results which are at least better than those of a pentanomial based multiplier. By applying our method to certain classes of finite fields we have gained a space complexity as n2 + H - 4 and a time complexity as TA + ([ log2(n-l) ]+3)rx which are better than the lowest space and time complexities of a pentanomial based multiplier found in literature. Therefore this multiplier can serve as an alternative in those finite fields in which no trinomial, all-one-polynomial or equally-spaced-polynomial exists

Neural Networks as Pseudorandom Number Generators

This thesis brings two disparate fields of research together; the fields of artificial neural networks and pseudorandom number generation. In it, we answer variations on the following question: can recurrent neural networks generate pseudorandom numbers? In doing so, we provide a new construction of an $n$-dimensional neural network that has period $2^n$, for all $n$. We also provide a technique for constructing neural networks based on the theory of shift register sequences. The randomness capabilities of these networks is then measured via the theoretical notion of computational indistinguishability and a battery of statistical tests. In particular, we show that neural networks cannot be pseudorandom number generators according to the theoretical definition of computational indistinguishability. We contrast this result by providing some neural networks that pass all of the tests in the SmallCrush battery of tests in the TestU01 testing suite

Positioning systems using families of binary sequences with low correlation

RESUMEN: El objetivo de este trabajo es el estudio de la aplicación de familias de secuencias binarias de baja correlación para su uso en sistemas de posicionamiento en tiempo real en interiores como por ejemplo en entornos industriales o de almacenamiento. Actualmente es un problemas abierto para el que se han propuesto distintas tecnologías como sistemas basados en visión artificial o en redes de sensores entre otros. En este proyecto se ha implementado un sistema de posicionamiento en interiores de bajos recursos por medio de secuencias binarias de baja correlación. La investigación se ha centrado en la revisión de las tecnologías existentes en el mercado, la búsqueda de las secuencias binarias más apropiadas y el estudio de sus propiedades. Siguiendo el modelo GPS como sistema de localización en exteriores, se ha construido un propotipo basado en placas Arduino. Nuestra propuesta codifica la información mediante secuencias Pseudo Noise, códigos Gold y Kasami. Posteriormente estas secuencias son transmitidas utilizando señales de ultrasonido. En el receptor, las señales recibidas se pueden procesar para obtener medidas como la distancia entre dispositivos y el ángulo de llegada entre otras.ABSTRACT: The aim of this project is the study of families of binary sequences of low correlation and its application to real-time indoor positioning systems in industrial or warehousing environments. Many different approaches based on different technologies such as artificial vision or sensor networks have been proposed for indoor localization but it still remains an open problem. In this work, we have implemented a low resources indoor positioning system over over a embedded system, that uses binary sequences of low correlation. The research has focused on existent technologies in the market, on the search of the most appropriate family of sequences and the study of their properties. Taking GPS as a reference model for outdoor localization, we have built a prototype based on Arduino boards. Our approach encodes messages with Pseudo Noise sequences, Gold and Kasami Codes. Afterwards, the sequences are transmitted as ultrasonic signals. Then, the receiver processes the incoming signal to obtain measures such as the distances between devices and the angle of arrival of the signal.Máster en Matemáticas y Computació