208 research outputs found

    Greedy vector quantization

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    We investigate the greedy version of the LpL^p-optimal vector quantization problem for an Rd\mathbb{R}^d-valued random vector X ⁣∈LpX\!\in L^p. We show the existence of a sequence (aN)N≄1(a_N)_{N\ge 1} such that aNa_N minimizes a↊∄min⁥1≀i≀N−1∣X−ai∣∧∣X−a∣∄Lpa\mapsto\big \|\min_{1\le i\le N-1}|X-a_i|\wedge |X-a|\big\|_{L^p} (LpL^p-mean quantization error at level NN induced by (a1,
,aN−1,a)(a_1,\ldots,a_{N-1},a)). We show that this sequence produces LpL^p-rate optimal NN-tuples a(N)=(a1,
,aN)a^{(N)}=(a_1,\ldots,a_{_N}) (i.e.i.e. the LpL^p-mean quantization error at level NN induced by a(N)a^{(N)} goes to 00 at rate N−1dN^{-\frac 1d}). Greedy optimal sequences also satisfy, under natural additional assumptions, the distortion mismatch property: the NN-tuples a(N)a^{(N)} remain rate optimal with respect to the LqL^q-norms, p≀q<p+dp\le q <p+d. Finally, we propose optimization methods to compute greedy sequences, adapted from usual Lloyd's I and Competitive Learning Vector Quantization procedures, either in their deterministic (implementable when d=1d=1) or stochastic versions.Comment: 31 pages, 4 figures, few typos corrected (now an extended version of an eponym paper to appear in Journal of Approximation

    A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-ÎŒm single-poly technology

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    This paper presents a CMOS 0.7-ÎŒm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.ComisiĂłn Interministerial de Ciencia y TecnologĂ­a TIC97-0580European Commission ESPRIT 879

    Quantization-based Bermudan option pricing in the FX world

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    This paper proposes two numerical solution based on Product Optimal Quan-tization for the pricing of Foreign Echange (FX) linked long term Bermudan options e.g. Bermudan Power Reverse Dual Currency options, where we take into account stochastic domestic and foreign interest rates on top of stochastic FX rate, hence we consider a 3-factor model. For these two numerical methods, we give an estimation of the L2L^2-error induced by such approximations and we illustrate them with market-based examples that highlight the speed of such methods

    Broadband Continuous-time MASH Sigma-Delta ADCs

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    The Impact of SAR-ADC Mismatch on Quantized Massive MU-MIMO Systems

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    Low-resolution analog-to-digital converters (ADCs) in massive multi-user (MU) multiple-input multiple-output (MIMO) wireless systems can significantly reduce the power, cost, and interconnect data rates of infrastructure basestations. Thus, recent research on the theory and algorithm sides has extensively focused on such architectures, but with idealistic quantization models. However, real-world ADCs do not behave like ideal quantizers, and are affected by fabrication mismatches. We analyze the impact of capacitor-array mismatches in successive approximation register (SAR) ADCs, which are widely used in wireless systems. We use Bussgang's decomposition to model the effects of such mismatches, and we analyze their impact on the performance of a single ADC. We then simulate a massive MU-MIMO system to demonstrate that capacitor mismatches should not be ignored, even in basestations that use low-resolution SAR ADCs.Comment: To be presented at Asilomar Conference on Signals, Systems, and Computers 202

    Tools for Automated Design of ΣΔ Modulators

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    We present a set of CAD tools to design ΣΔ modulators. They use statistical optimization to calculate optimum specifications for the building blocks used in the modulators, and optimum sizes for the components in these blocks. Optimization procedures at the modulator level are equation-based, while procedures at the cell level are simulation-based. The toolset incorporates also an advanced ΣΔ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: 1) a 17bit@40kHz output rate fourth-order low-pass modulator; and 2) a [email protected] central freq@10kHz bandwidth band-pass modulator. The first uses SC fully-differential circuits in a 1.2ÎŒm CMOS double-metal double-poly technology. The second uses SI fully-differential circuits in a 0.8ÎŒm CMOS double-metal single-poly technology.This work has been supported by the CEE ESPRIT Program in the framework of the Project #8795 (AMFIS).Peer reviewe

    Tools for Automated Design of ΣΔ Modulators

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    We present a set of CAD tools to design ΣΔ modulators. They use statistical optimization to calculate optimum specifications for the building blocks used in the modulators, and optimum sizes for the components in these blocks. Optimization procedures at the modulator level are equation-based, while procedures at the cell level are simulation-based. The toolset incorporates also an advanced ΣΔ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: 1) a 17bit@40kHz output rate fourth-order low-pass modulator; and 2) a [email protected] central freq@10kHz bandwidth band-pass modulator. The first uses SC fully-differential circuits in a 1.2ÎŒm CMOS double-metal double-poly technology. The second uses SI fully-differential circuits in a 0.8ÎŒm CMOS double-metal single-poly technology
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