27,512 research outputs found
Accepting Hybrid Networks of Evolutionary Processors
We consider time complexity classes defined on accepting hybrid
networks of evolutionary processors (AHNEP) similarly to the classical
time complexity classes defined on the standard computing model
of Turing machine. By definition, AHNEPs are deterministic. We prove
that the classical complexity class NP equals the set of languages accepted
by AHNEPs in polynomial time
AND and/or OR: Uniform Polynomial-Size Circuits
We investigate the complexity of uniform OR circuits and AND circuits of
polynomial-size and depth. As their name suggests, OR circuits have OR gates as
their computation gates, as well as the usual input, output and constant (0/1)
gates. As is the norm for Boolean circuits, our circuits have multiple sink
gates, which implies that an OR circuit computes an OR function on some subset
of its input variables. Determining that subset amounts to solving a number of
reachability questions on a polynomial-size directed graph (which input gates
are connected to the output gate?), taken from a very sparse set of graphs.
However, it is not obvious whether or not this (restricted) reachability
problem can be solved, by say, uniform AC^0 circuits (constant depth,
polynomial-size, AND, OR, NOT gates). This is one reason why characterizing the
power of these simple-looking circuits in terms of uniform classes turns out to
be intriguing. Another is that the model itself seems particularly natural and
worthy of study.
Our goal is the systematic characterization of uniform polynomial-size OR
circuits, and AND circuits, in terms of known uniform machine-based complexity
classes. In particular, we consider the languages reducible to such uniform
families of OR circuits, and AND circuits, under a variety of reduction types.
We give upper and lower bounds on the computational power of these language
classes. We find that these complexity classes are closely related to tallyNL,
the set of unary languages within NL, and to sets reducible to tallyNL.
Specifically, for a variety of types of reductions (many-one, conjunctive truth
table, disjunctive truth table, truth table, Turing) we give characterizations
of languages reducible to OR circuit classes in terms of languages reducible to
tallyNL classes. Then, some of these OR classes are shown to coincide, and some
are proven to be distinct. We give analogous results for AND circuits. Finally,
for many of our OR circuit classes, and analogous AND circuit classes, we prove
whether or not the two classes coincide, although we leave one such inclusion
open.Comment: In Proceedings MCU 2013, arXiv:1309.104
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