3,901 research outputs found
An Automated Design-flow for FPGA-based Sequential Simulation
In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.\u
Emulating and evaluating hybrid memory for managed languages on NUMA hardware
Non-volatile memory (NVM) has the potential to become a mainstream memory technology and challenge DRAM. Researchers evaluating the speed, endurance, and abstractions of hybrid memories with DRAM and NVM typically use simulation, making it easy to evaluate the impact of different hardware technologies and parameters. Simulation is, however, extremely slow, limiting the applications and datasets in the evaluation. Simulation also precludes critical workloads, especially those written in managed languages such as Java and C#. Good methodology embraces a variety of techniques for evaluating new ideas, expanding the experimental scope, and uncovering new insights.
This paper introduces a platform to emulate hybrid memory for managed languages using commodity NUMA servers. Emulation complements simulation but offers richer software experimentation. We use a thread-local socket to emulate DRAM and a remote socket to emulate NVM. We use standard C library routines to allocate heap memory on the DRAM and NVM sockets for use with explicit memory management or garbage collection. We evaluate the emulator using various configurations of write-rationing garbage collectors that improve NVM lifetimes by limiting writes to NVM, using 15 applications and various datasets and workload configurations. We show emulation and simulation confirm each other's trends in terms of writes to NVM for different software configurations, increasing our confidence in predicting future system effects. Emulation brings novel insights, such as the non-linear effects of multi-programmed workloads on NVM writes, and that Java applications write significantly more than their C++ equivalents. We make our software infrastructure publicly available to advance the evaluation of novel memory management schemes on hybrid memories
Exploring Application Performance on Emerging Hybrid-Memory Supercomputers
Next-generation supercomputers will feature more hierarchical and
heterogeneous memory systems with different memory technologies working
side-by-side. A critical question is whether at large scale existing HPC
applications and emerging data-analytics workloads will have performance
improvement or degradation on these systems. We propose a systematic and fair
methodology to identify the trend of application performance on emerging
hybrid-memory systems. We model the memory system of next-generation
supercomputers as a combination of "fast" and "slow" memories. We then analyze
performance and dynamic execution characteristics of a variety of workloads,
from traditional scientific applications to emerging data analytics to compare
traditional and hybrid-memory systems. Our results show that data analytics
applications can clearly benefit from the new system design, especially at
large scale. Moreover, hybrid-memory systems do not penalize traditional
scientific applications, which may also show performance improvement.Comment: 18th International Conference on High Performance Computing and
Communications, IEEE, 201
Teaching Memory Circuit Elements via Experiment-Based Learning
The class of memory circuit elements which comprises memristive,
memcapacitive, and meminductive systems, is gaining considerable attention in a
broad range of disciplines. This is due to the enormous flexibility these
elements provide in solving diverse problems in analog/neuromorphic and
digital/quantum computation; the possibility to use them in an integrated
computing-memory paradigm, massively-parallel solution of different
optimization problems, learning, neural networks, etc. The time is therefore
ripe to introduce these elements to the next generation of physicists and
engineers with appropriate teaching tools that can be easily implemented in
undergraduate teaching laboratories. In this paper, we suggest the use of
easy-to-build emulators to provide a hands-on experience for the students to
learn the fundamental properties and realize several applications of these
memelements. We provide explicit examples of problems that could be tackled
with these emulators that range in difficulty from the demonstration of the
basic properties of memristive, memcapacitive, and meminductive systems to
logic/computation and cross-bar memory. The emulators can be built from
off-the-shelf components, with a total cost of a few tens of dollars, thus
providing a relatively inexpensive platform for the implementation of these
exercises in the classroom. We anticipate that this experiment-based learning
can be easily adopted and expanded by the instructors with many more case
studies.Comment: IEEE Circuits and Systems Magazine (in press
Simple Floating Voltage-Controlled Memductor Emulator for Analog Applications
The topic of memristive circuits is a novel topic in circuit theory that has become of great importance due to its unique behavior which is useful in different applications. But since there is a lack of memristor samples, a memristor emulator is used instead of a solid state memristor. In this paper, a new simple floating voltage-controlled memductor emulator is introduced which is implemented using commercial off the shelf (COTS) realization. The mathematical modeling of the proposed circuit is derived to match the theoretical model. The proposed circuit is tested experimentally using different excitation signals such as sinusoidal, square, and triangular waves showing an excellent matching with previously reported simulations
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