451 research outputs found
A Signal Distribution Network for Sequential Quantum-dot Cellular Automata Systems
The authors describe a signal distribution network for sequential systems constructed using the Quantum-dot Cellular Automata (QCA) computing paradigm. This network promises to enable the construction of arbitrarily complex QCA sequential systems in which all wire crossings are performed using nearest neighbor interactions, which will improve the thermal behavior of QCA systems as well as their resistance to stray charge and fabrication imperfections. The new sequential signal distribution network is demonstrated by the complete design and simulation of a two-bit counter, a three-bit counter, and a pattern detection circuit
Removing Redundant Logic Pathways in Polymorphic Circuits
Evaluating the quality of software and circuit obfuscators is a research goal of great interest. However, there exists little research about evaluation of obfuscation effectiveness through analyzing and investigating redundancies found in the obfuscated variants. In this research, we consider programs represented as structural combinational circuits and then analyze obfuscated variants of those circuits through a tool that produces functionally equivalent variants based on subcircuit selection and replacement. We then consider how Boolean logic and reduction affects the size and levelization of circuit variants, giving us a concrete metric by which to consider obfuscation effectiveness. To accomplish these goals, we create an experimental environment based on a set of predefined circuits, a set of predefined algorithms which produce variants of those circuits, and a collection of logic reduction techniques and tools. We build logic reduction techniques using predefined patterns and predefined functions expressed as truth tables. As a contribution, we characterize and evaluate the effectiveness of obfuscating algorithms based on these reduction techniques. We show, for the circuits we observe, optimization on size is affected by ordering of the specific reduction patterns and functions. We also show, for the circuits we observe, reduction is affected by the specific obfuscating algorithm used to produce the variant. Based on these results, we provide a promising measurement of interest to compare both circuit variants and obfuscating algorithms
Transient error mitigation by means of approximate logic circuits
Mención Internacional en el título de doctorThe technological advances in the manufacturing of electronic circuits have allowed to
greatly improve their performance, but they have also increased the sensitivity of electronic
devices to radiation-induced errors. Among them, the most common effects are
the SEEs, i.e., electrical perturbations provoked by the strike of high-energy particles,
which may modify the internal state of a memory element (SEU) or generate erroneous
transient pulses (SET), among other effects. These events pose a threat for the reliability
of electronic circuits, and therefore fault-tolerance techniques must be applied to
deal with them.
The most common fault-tolerance techniques are based in full replication (DWC or
TMR). These techniques are able to cover a wide range of failure mechanisms present
in electronic circuits. However, they suffer from high overheads in terms of area and
power consumption. For this reason, lighter alternatives are often sought at the expense
of slightly reducing reliability for the least critical circuit sections. In this context a new
paradigm of electronic design is emerging, known as approximate computing, which
is based on improving the circuit performance in change of slight modifications of the
intended functionality. This is an interesting approach for the design of lightweight
fault-tolerant solutions, which has not been yet studied in depth.
The main goal of this thesis consists in developing new lightweight fault-tolerant
techniques with partial replication, by means of approximate logic circuits. These
circuits can be designed with great flexibility. This way, the level of protection as
well as the overheads can be adjusted at will depending on the necessities of each
application. However, finding optimal approximate circuits for a given application is
still a challenge.
In this thesis a method for approximate circuit generation is proposed, denoted
as fault approximation, which consists in assigning constant logic values to specific
circuit lines. On the other hand, several criteria are developed to generate the most
suitable approximate circuits for each application, by using this fault approximation
mechanism. These criteria are based on the idea of approximating the least testable
sections of circuits, which allows reducing overheads while minimising the loss of reliability.
Therefore, in this thesis the selection of approximations is linked to testability
measures.
The first criterion for fault selection developed in this thesis uses static testability
measures. The approximations are generated from the results of a fault simulation of
the target circuit, and from a user-specified testability threshold. The amount of approximated
faults depends on the chosen threshold, which allows to generate approximate circuits with different performances. Although this approach was initially intended for
combinational circuits, an extension to sequential circuits has been performed as well,
by considering the flip-flops as both inputs and outputs of the combinational part of
the circuit. The experimental results show that this technique achieves a wide scalability,
and an acceptable trade-off between reliability versus overheads. In addition, its
computational complexity is very low.
However, the selection criterion based in static testability measures has some drawbacks.
Adjusting the performance of the generated approximate circuits by means of
the approximation threshold is not intuitive, and the static testability measures do not
take into account the changes as long as faults are approximated. Therefore, an alternative
criterion is proposed, which is based on dynamic testability measures. With this
criterion, the testability of each fault is computed by means of an implication-based
probability analysis. The probabilities are updated with each new approximated fault,
in such a way that on each iteration the most beneficial approximation is chosen, that
is, the fault with the lowest probability. In addition, the computed probabilities allow
to estimate the level of protection against faults that the generated approximate circuits
provide. Therefore, it is possible to generate circuits which stick to a target error rate.
By modifying this target, circuits with different performances can be obtained. The
experimental results show that this new approach is able to stick to the target error rate
with reasonably good precision. In addition, the approximate circuits generated with
this technique show better performance than with the approach based in static testability
measures. In addition, the fault implications have been reused too in order to
implement a new type of logic transformation, which consists in substituting functionally
similar nodes.
Once the fault selection criteria have been developed, they are applied to different
scenarios. First, an extension of the proposed techniques to FPGAs is performed,
taking into account the particularities of this kind of circuits. This approach has been
validated by means of radiation experiments, which show that a partial replication with
approximate circuits can be even more robust than a full replication approach, because
a smaller area reduces the probability of SEE occurrence. Besides, the proposed
techniques have been applied to a real application circuit as well, in particular to the
microprocessor ARM Cortex M0. A set of software benchmarks is used to generate
the required testability measures. Finally, a comparative study of the proposed approaches
with approximate circuit generation by means of evolutive techniques have
been performed. These approaches make use of a high computational capacity to generate
multiple circuits by trial-and-error, thus reducing the possibility of falling into
local minima. The experimental results demonstrate that the circuits generated with
evolutive approaches are slightly better in performance than the circuits generated with
the techniques here proposed, although with a much higher computational effort.
In summary, several original fault mitigation techniques with approximate logic
circuits are proposed. These approaches are demonstrated in various scenarios, showing
that the scalability and adaptability to the requirements of each application are their
main virtuesLos avances tecnológicos en la fabricación de circuitos electrónicos han permitido mejorar
en gran medida sus prestaciones, pero también han incrementado la sensibilidad
de los mismos a los errores provocados por la radiación. Entre ellos, los más comunes
son los SEEs, perturbaciones eléctricas causadas por el impacto de partículas de alta
energía, que entre otros efectos pueden modificar el estado de los elementos de memoria
(SEU) o generar pulsos transitorios de valor erróneo (SET). Estos eventos suponen
un riesgo para la fiabilidad de los circuitos electrónicos, por lo que deben ser tratados
mediante técnicas de tolerancia a fallos.
Las técnicas de tolerancia a fallos más comunes se basan en la replicación completa
del circuito (DWC o TMR). Estas técnicas son capaces de cubrir una amplia variedad
de modos de fallo presentes en los circuitos electrónicos. Sin embargo, presentan un
elevado sobrecoste en área y consumo. Por ello, a menudo se buscan alternativas más
ligeras, aunque no tan efectivas, basadas en una replicación parcial. En este contexto
surge una nueva filosofía de diseño electrónico, conocida como computación aproximada,
basada en mejorar las prestaciones de un diseño a cambio de ligeras modificaciones
de la funcionalidad prevista. Es un enfoque atractivo y poco explorado para el diseño
de soluciones ligeras de tolerancia a fallos.
El objetivo de esta tesis consiste en desarrollar nuevas técnicas ligeras de tolerancia
a fallos por replicación parcial, mediante el uso de circuitos lógicos aproximados. Estos
circuitos se pueden diseñar con una gran flexibilidad. De este forma, tanto el nivel de
protección como el sobrecoste se pueden regular libremente en función de los requisitos
de cada aplicación. Sin embargo, encontrar los circuitos aproximados óptimos para
cada aplicación es actualmente un reto.
En la presente tesis se propone un método para generar circuitos aproximados, denominado
aproximación de fallos, consistente en asignar constantes lógicas a ciertas
líneas del circuito. Por otro lado, se desarrollan varios criterios de selección para, mediante
este mecanismo, generar los circuitos aproximados más adecuados para cada
aplicación. Estos criterios se basan en la idea de aproximar las secciones menos testables
del circuito, lo que permite reducir los sobrecostes minimizando la perdida de
fiabilidad. Por tanto, en esta tesis la selección de aproximaciones se realiza a partir de
medidas de testabilidad.
El primer criterio de selección de fallos desarrollado en la presente tesis hace uso de
medidas de testabilidad estáticas. Las aproximaciones se generan a partir de los resultados
de una simulación de fallos del circuito objetivo, y de un umbral de testabilidad
especificado por el usuario. La cantidad de fallos aproximados depende del umbral escogido, lo que permite generar circuitos aproximados con diferentes prestaciones.
Aunque inicialmente este método ha sido concebido para circuitos combinacionales,
también se ha realizado una extensión a circuitos secuenciales, considerando los biestables
como entradas y salidas de la parte combinacional del circuito. Los resultados
experimentales demuestran que esta técnica consigue una buena escalabilidad, y unas
prestaciones de coste frente a fiabilidad aceptables. Además, tiene un coste computacional
muy bajo.
Sin embargo, el criterio de selección basado en medidas estáticas presenta algunos
inconvenientes. No resulta intuitivo ajustar las prestaciones de los circuitos aproximados
a partir de un umbral de testabilidad, y las medidas estáticas no tienen en cuenta los
cambios producidos a medida que se van aproximando fallos. Por ello, se propone un
criterio alternativo de selección de fallos, basado en medidas de testabilidad dinámicas.
Con este criterio, la testabilidad de cada fallo se calcula mediante un análisis de probabilidades
basado en implicaciones. Las probabilidades se actualizan con cada nuevo
fallo aproximado, de forma que en cada iteración se elige la aproximación más favorable,
es decir, el fallo con menor probabilidad. Además, las probabilidades calculadas
permiten estimar la protección frente a fallos que ofrecen los circuitos aproximados
generados, por lo que es posible generar circuitos que se ajusten a una tasa de fallos
objetivo. Modificando esta tasa se obtienen circuitos aproximados con diferentes prestaciones.
Los resultados experimentales muestran que este método es capaz de ajustarse
razonablemente bien a la tasa de fallos objetivo. Además, los circuitos generados
con esta técnica muestran mejores prestaciones que con el método basado en medidas
estáticas. También se han aprovechado las implicaciones de fallos para implementar
un nuevo tipo de transformación lógica, consistente en sustituir nodos funcionalmente
similares.
Una vez desarrollados los criterios de selección de fallos, se aplican a distintos
campos. En primer lugar, se hace una extensión de las técnicas propuestas para FPGAs,
teniendo en cuenta las particularidades de este tipo de circuitos. Esta técnica se ha validado
mediante experimentos de radiación, los cuales demuestran que una replicación
parcial con circuitos aproximados puede ser incluso más robusta que una replicación
completa, ya que un área más pequeña reduce la probabilidad de SEEs. Por otro lado,
también se han aplicado las técnicas propuestas en esta tesis a un circuito de aplicación
real, el microprocesador ARM Cortex M0, utilizando un conjunto de benchmarks
software para generar las medidas de testabilidad necesarias. Por ´último, se realiza un
estudio comparativo de las técnicas desarrolladas con la generación de circuitos aproximados
mediante técnicas evolutivas. Estas técnicas hacen uso de una gran capacidad
de cálculo para generar múltiples circuitos mediante ensayo y error, reduciendo la posibilidad
de caer en algún mínimo local. Los resultados confirman que, en efecto, los
circuitos generados mediante técnicas evolutivas son ligeramente mejores en prestaciones
que con las técnicas aquí propuestas, pero con un coste computacional mucho
mayor.
En definitiva, se proponen varias técnicas originales de mitigación de fallos mediante
circuitos aproximados. Se demuestra que estas técnicas tienen diversas aplicaciones,
haciendo de la flexibilidad y adaptabilidad a los requisitos de cada aplicación
sus principales virtudes.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Raoul Velazco.- Secretario: Almudena Lindoso Muñoz.- Vocal: Jaume Segura Fuste
Introduction to Logic Circuits & Logic Design with VHDL
The overall goal of this book is to fill a void that has appeared in the instruction of digital circuits over
the past decade due to the rapid abstraction of system design. Up until the mid-1980s, digital circuits
were designed using classical techniques. Classical techniques relied heavily on manual design
practices for the synthesis, minimization, and interfacing of digital systems. Corresponding to this design
style, academic textbooks were developed that taught classical digital design techniques. Around 1990,
large-scale digital systems began being designed using hardware description languages (HDL) and
automated synthesis tools. Broad-scale adoption of this modern design approach spread through the
industry during this decade. Around 2000, hardware description languages and the modern digital
design approach began to be taught in universities, mainly at the senior and graduate level. There
were a variety of reasons that the modern digital design approach did not penetrate the lower levels of
academia during this time. First, the design and simulation tools were difficult to use and overwhelmed
freshman and sophomore students. Second, the ability to implement the designs in a laboratory setting
was infeasible. The modern design tools at the time were targeted at custom integrated circuits, which
are cost- and time-prohibitive to implement in a university setting. Between 2000 and 2005, rapid
advances in programmable logic and design tools allowed the modern digital design approach to be
implemented in a university setting, even in lower-level courses. This allowed students to learn the
modern design approach based on HDLs and prototype their designs in real hardware, mainly field
programmable gate arrays (FPGAs). This spurred an abundance of textbooks to be authored teaching
hardware description languages and higher levels of design abstraction. This trend has continued until
today. While abstraction is a critical tool for engineering design, the rapid movement toward teaching only
the modern digital design techniques has left a void for freshman- and sophomore-level courses in digital
circuitry. Legacy textbooks that teach the classical design approach are outdated and do not contain
sufficient coverage of HDLs to prepare the students for follow-on classes. Newer textbooks that teach
the modern digital design approach move immediately into high-level behavioral modeling with minimal
or no coverage of the underlying hardware used to implement the systems. As a result, students are not
being provided the resources to understand the fundamental hardware theory that lies beneath the
modern abstraction such as interfacing, gate-level implementation, and technology optimization.
Students moving too rapidly into high levels of abstraction have little understanding of what is going
on when they click the “compile and synthesize” button of their design tool. This leads to graduates who
can model a breadth of different systems in an HDL but have no depth into how the system is
implemented in hardware. This becomes problematic when an issue arises in a real design and there
is no foundational knowledge for the students to fall back on in order to debug the problem
Introduction to Logic Circuits & Logic Design with Verilog
The overall goal of this book is to fill a void that has appeared in the instruction of digital circuits over
the past decade due to the rapid abstraction of system design. Up until the mid-1980s, digital circuits
were designed using classical techniques. Classical techniques relied heavily on manual design
practices for the synthesis, minimization, and interfacing of digital systems. Corresponding to this design
style, academic textbooks were developed that taught classical digital design techniques. Around 1990,
large-scale digital systems began being designed using hardware description languages (HDL) and
automated synthesis tools. Broad-scale adoption of this modern design approach spread through the
industry during this decade. Around 2000, hardware description languages and the modern digital
design approach began to be taught in universities, mainly at the senior and graduate level. There
were a variety of reasons that the modern digital design approach did not penetrate the lower levels of
academia during this time. First, the design and simulation tools were difficult to use and overwhelmed
freshman and sophomore students. Second, the ability to implement the designs in a laboratory setting
was infeasible. The modern design tools at the time were targeted at custom integrated circuits, which
are cost- and time-prohibitive to implement in a university setting. Between 2000 and 2005, rapid
advances in programmable logic and design tools allowed the modern digital design approach to be
implemented in a university setting, even in lower-level courses. This allowed students to learn the
modern design approach based on HDLs and prototype their designs in real hardware, mainly fieldprogrammable gate arrays (FPGAs). This spurred an abundance of textbooks to be authored, teaching
hardware description languages and higher levels of design abstraction. This trend has continued until
today. While abstraction is a critical tool for engineering design, the rapid movement toward teaching only
the modern digital design techniques has left a void for freshman- and sophomore-level courses in digital
circuitry. Legacy textbooks that teach the classical design approach are outdated and do not contain
sufficient coverage of HDLs to prepare the students for follow-on classes. Newer textbooks that teach
the modern digital design approach move immediately into high-level behavioral modeling with minimal
or no coverage of the underlying hardware used to implement the systems. As a result, students are not
being provided the resources to understand the fundamental hardware theory that lies beneath the
modern abstraction such as interfacing, gate-level implementation, and technology optimization.
Students moving too rapidly into high levels of abstraction have little understanding of what is going
on when they click the “compile and synthesize” button of their design tool. This leads to graduates who
can model a breadth of different systems in an HDL but have no depth into how the system is
implemented in hardware. This becomes problematic when an issue arises in a real design and there
is no foundational knowledge for the students to fall back on in order to debug the problem
Energy-Efficient Digital Circuit Design using Threshold Logic Gates
abstract: Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. As a result, a multitude of methods to reduce power without sacrificing performance have been proposed. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, leakage and area. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical.
The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flipflop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flipflops and parts of their logic cones with PNAND cells is described. The resulting \hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation.
Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy-delay product compared to conventional FPGA using well known FPGA modeling tool called VPR.
Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flipflops is described. This clock skewing method improves the area and power of the ASIC circuits by increasing slack on timing paths. An additional advantage of this method is the elimination of hold time violation on given short paths.
Several circuit design methodologies such as retiming and asynchronous circuit design can use the proposed threshold logic gate effectively. Therefore, the use of threshold logic flipflops in conventional design methodologies opens new avenues of research towards more energy-efficient circuits.Dissertation/ThesisDoctoral Dissertation Computer Science 201
Form Follows Function: A Different Approach to Neuron Connectivity
It may be possible to discover much of the organization of synaptic
connections in nervous systems by designing simple logic circuits that can
perform a single, biologically advantageous function. This method has led to
neuronal networks that can generate neural correlates of phenomena central to
color vision, olfaction, short-term memory, and brain waves. One of the network
designs is a family of general information processors that exhibit major
features of cerebral cortex physiology and anatomy. A similar logic circuit
approach applied to two primitive ganglia that have been studied extensively
led to discoveries of how the ganglia can produce lobster peristaltic action
and lamprey locomotion.
For each network design, all neurons, connections, and types of connections
are shown explicitly. The neurons' operation depends only on explicitly stated,
minimal properties of excitement and inhibition. This operation is dynamic in
the sense that the level of neuron activity is the only cellular change, making
the networks' operation consistent with the speed of most brain functions.
Conclusions that the networks can generate neural correlates of known phenomena
are not claims; they are theorems that follow from the models' explicit
architectures and minimal neuron capabilities.
The logic circuit designs can be implemented with electronic components. A
few of the designs are apparently new to engineering, filling gaps and
providing improvements in well-known families of logic circuits. A novel
transformation can convert certain electronic logic circuit designs to neuronal
network designs, and vice versa
Constraint solving over multi-valued logics - application to digital circuits
Due to usage conditions, hazardous environments or intentional causes, physical and virtual systems are subject to faults in their components, which may affect their overall behaviour. In a ‘black-box’ agent modelled by a set of propositional logic rules, in which just a subset of components is externally visible, such faults may only be recognised by examining some output function of the agent. A (fault-free) model of the agent’s system provides the expected output given some input. If the real output differs from that predicted output, then the system is faulty. However, some faults may only become apparent in the system output when appropriate inputs are given. A number of problems regarding both testing and diagnosis thus arise, such as testing a fault, testing the whole system, finding possible faults and differentiating them to locate the correct one. The corresponding optimisation problems of finding solutions that require minimum resources are also very relevant in industry, as is minimal diagnosis. In this dissertation we use a well established set of benchmark circuits to address such diagnostic related problems and propose and develop models with different logics that we formalise and generalise as much as possible. We also prove that all techniques generalise to agents and to multiple faults. The developed multi-valued logics extend the usual Boolean logic (suitable for faultfree models) by encoding values with some dependency (usually on faults). Such logics thus allow modelling an arbitrary number of diagnostic theories. Each problem is subsequently solved with CLP solvers that we implement and discuss, together with a new efficient search technique that we present. We compare our results with other approaches such as SAT (that require substantial duplication of circuits), showing the effectiveness of constraints over multi-valued logics, and also the adequacy of a general set constraint solver (with special inferences over set functions such as cardinality) on other problems. In addition, for an optimisation problem, we integrate local search with a constructive approach (branch-and-bound) using a variety of logics to improve an existing efficient tool based on SAT and ILP
Doctor of Philosophy
dissertationElasticity is a design paradigm in which circuits can tolerate arbitrary latency/delay variations in their computation units as well as communication channels. Creating elastic (both synchronous and asynchronous) designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations have been suggested in the literature and each of these require a handshake control network (examples include synchronous elasticization and desynchronization). Elastic control network area and power overheads may become prohibitive. This dissertation investigates different optimization avenues to reduce these overheads without sacrificing the control network performance. First, an algorithm and a tool, CNG, is introduced that generates a control network with minimal total number of join and fork control steering units. Synchronous Elastic FLow (SELF) is a handshake protocol used over synchronous elastic designs. Comparing to its standard eager implementation (that uses eager forks - EForks), lazy SELF can consume less power and area. However, it typically suff ers from combinational cycles and can have inferior performance in some systems. Hence, lazy SELF has been rarely studied in the literature. This work formally and exhaustively investigates the specifi cations, diff erent implementations, and verifi cation of the lazy SELF protocol. Furthermore, several new and existing lazy designs are mapped to hybrid eager/lazy imple-mentations that retain the performance advantage of the eager design but have power and area advantages of lazy implementations, and are combinational-cycle free. This work also introduces a novel ultra simple fork (USFork) design. The USFork has two advantages over lazy forks: it is composed of simpler logic (just wires) and does not form combinational cycles. The conditions under which an EFork can be replaced by a USFork without any performance loss are formally derived. The last optimization avenue discussed in this dissertation is Elastic Bu er Controller (EBC) merging. In a typical synchronous elastic control network, some EBCs may activate their corresponding latches at similar schedules. This work provides a framework for fi nding and merging such controllers in any control network; including open networks (i.e., when the environment abstract is not available or required to be flexible) as well as networks incorporating variable latency units. Replacing EForks with USForks under some equivalence conditions as well as EBC merging have been fully automated in a tool, HGEN. The impact of this work will help achieve elasticity at a reduced cost. It will broaden the class of circuits that can be elasticized with acceptable overhead (circuits that designers would otherwise nd it too expensive to elasticize). In a MiniMIPS processor case study, comparing to a basic control network implementation, the optimization techniques of this dissertation accumulatively achieve reductions in the control network area, dynamic, and leakage power of 73.2%, 68.6%, and 69.1%, respectively
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