Custom Integrated Circuits

Contains reports on twelve research projects.Analog Devices, Inc.International Business Machines, Inc.Joint Services Electronics Program (Contract DAAL03-86-K-0002)Joint Services Electronics Program (Contract DAAL03-89-C-0001)U.S. Air Force - Office of Scientific Research (Grant AFOSR 86-0164)Rockwell International CorporationOKI Semiconductor, Inc.U.S. Navy - Office of Naval Research (Contract N00014-81-K-0742)Charles Stark Draper LaboratoryNational Science Foundation (Grant MIP 84-07285)National Science Foundation (Grant MIP 87-14969)Battelle LaboratoriesNational Science Foundation (Grant MIP 88-14612)DuPont CorporationDefense Advanced Research Projects Agency/U.S. Navy - Office of Naval Research (Contract N00014-87-K-0825)American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation (Grant MIP-88-58764

Efficient state reduction methods for PLA-based sequential circuits

Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are shown. The area of the PLA implementation of the combinational component and the design time are used as figures of merit. The comparison of such parameters, when the state reduction step is included in the design process and when it is not, suggests that fast state-reduction heuristics should be implemented within FSM automatic synthesis systems

Fault detection on sequential machines

This paper presents an algorithm for deriving an optimum test sequence for detecting faults in a synchronous machine. In this study, the flow table is used as a tool to generate the fault detection tests. The fault stuck-at-1 (or stuck-at-0 ) is said to be present when a permanent signal valued 1 (or 0) appears on a component of the machine. Only single faults are treated . The result of the procedure is one or more test sequences guaranteed to detect a set of faults (Fp). First, sequential machines with feedback lines as memory elements are considered . Then the memory elements are changed to R-S flip-flops. Finally, several suggestions for further work are made --Abstract, Page ii

Custom Integrated Circuits

Contains reports on nine research projects.Analog Devices, Inc.International Business Machines CorporationJoint Services Electronics Program Contract DAAL03-89-C-0001U.S. Air Force - Office of Scientific Research Contract AFOSR 86-0164BDuPont CorporationNational Science Foundation Grant MIP 88-14612U.S. Navy - Office of Naval Research Contract N00014-87-K-0825American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation Grant MIP 88-5876

Custom Integrated Circuits

Contains reports on ten research projects.Analog Devices, Inc.IBM CorporationNational Science Foundation/Defense Advanced Research Projects Agency Grant MIP 88-14612Analog Devices Career Development Assistant ProfessorshipU.S. Navy - Office of Naval Research Contract N0014-87-K-0825AT&TDigital Equipment CorporationNational Science Foundation Grant MIP 88-5876

Synthesis and Optimization of Reversible Circuits - A Survey

Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms --- search-based, cycle-based, transformation-based, and BDD-based --- as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table

Algorithm for Tant Synthesis and Its Sequential Application

Electrical Engineerin

Controllability Analysis and Control Design of Biological Systems Modeled by Boolean Networks

Cell signaling networks are often modeled using ordinary differential equations (ODEs), which represent network components with continuous variables. However, parameters such as reaction rate constants are needed for ODEs are not always available or known, and discrete approaches such as Boolean networks (BNs) are used in such cases. BNs have been applied in the past, in particular, as means to determine network steady states. The goal of this work is to explore the use of BNs from a control theory point of view, that to help manipulate biological systems more efficiently. In this thesis, we propose two methods to analyze and design control strategies for BNs. The first method, based on the algebraic state-space representation of BNs, consist of defining control strategies to reach predetermined states, namely, given a desired output, find all possible system state transition trajectories to that output, and design an input sequence leading to it. The second method aims at introducing an alternative and an extension of the first method in the sense that it offers broader possibilities for the representation of time and it is scalable to BNs of bigger size. This method is based on binary decision diagrams (BDDs), a data structure very efficient to represent logical functions and allow us to relate outputs of a network to its inputs no matter how many layers it contains and whether or not it has a cyclic structure